物联网设备是数字化时代实现“万物互联”的硬件基础，传统的无线收发机芯片依赖电池供电，电池更换和维护成本成为物联网设备大规模部署的瓶颈。无线能量采集供电可以支持物联网设备在无电池条件下实现大规模、全场景、低成本部署，但是提供的电压较低。因此，低电压的无线收发机芯片是物联网设备支持无线能量采集供电的关键技术。本文面向低电压条件下低功耗无线收发机芯片的设计，系统分析了收发机在低电压下的设计挑战，通过电路和系统的创新，实现了支持0.5V超低电压工作的蓝牙低功耗（BLE）收发机，完成了锁相环、发射机和收发机等四款芯片的设计与测试。针对低电压下小数锁相环量化噪声消除的难题，本文提出了内嵌FIR滤波器的注入锁定相位域滤波器，在无需非线性校准的条件下实现对量化噪声的有效抑制，且适合低电压工作。滤波器功能通过BBPLL在65nm CMOS下流片验证，将锁相环带内相位噪声和带外小数杂散分别提升25dB和10dB。针对低电压下小数锁相环鉴相和量化噪声消除的难题，本文提出了时钟交织触发器型鉴相器（TI-FFPD）和电压模式相位插值器（VPI）两个创新性结构。TI-FFPD通过基于占空比的鉴相和共模电压纹波抵消，实现了高线性度和低参考杂散。VPI采用无源器件占主导的电路实现电压域相位插值。混合型小数锁相环采用28nm CMOS工艺实现，支持0.5V的电源电压，功耗为0.78mW，具有优良的抖动和杂散性能。针对低电压下发射机的效率提升和性能优化，本文提出了基于RDAC的开环电压控制，改混合型锁相环的参考杂散；提出了具有共享偏置电阻的切换电流源（SCS）振荡器和用于E/F2类功率放大器的占空比控制方法。发射机采用65nm CMOS工艺实现，在0.6V的电源电压和0dBm的输出功率下实现25.1%的系统效率，并满足BLE指标要求。针对低电压下接收机的功耗优化，本文提出基于延时的1-bit解调架构，实现了对GFSK调制简单高效的解调。针对低电压下模拟基带电路的电压裕度不足的问题，提出了采用双共模反馈环路的电压模式两级OTA，在无偏置电流的条件下提供了足够的增益和稳定性。采用28nm CMOS实现了完整的BLE收发机，支持0.5V低电压工作，满足BLE指标要求，接收机功耗仅需1.5mW。综上所述，本文面向低电压条件下锁相环、发射机和接收机的设计，层层递进，从电路到系统层面进行创新，提出了适合低电压工作的电路模块和系统架构，有效降低了收发机的功耗，提升了系统效率，为突破低电压条件下低功耗收发机的性能瓶颈做出了一定的贡献。

Low-power Internet of Things (IoT) devices serve as the hardware foundation for realizing "connectivity of everything" in the digital era. Traditional wireless transceiver chips rely on battery power, and the replacement and maintenance of batteries have become a bottleneck for large-scale IoT deployment. Wireless energy harvesting can support large-scale, all-scenario, and low-cost deployment of battery-free IoT devices. However, the supply voltage it can provide is relatively low. Therefore, low-voltage wireless transceiver chips are the key technology for IoT devices powered by wireless energy harvesting. Low-voltage design not only avoids the efficiency loss caused by voltage boosters, but also helps improve the transconductance efficiency of analog circuits and reduce the dynamic power consumption of digital circuits. However, designing circuits such as phase-locked loops (PLLs) and analog basebands under low-voltage conditions presents significant challenges, limiting the overall performance of the transceiver.This dissertation addresses the design challenges of low-power wireless transceiver chips under low-voltage conditions. It systematically analyzes the challenges of transceiver design under low voltage, including quantization noise suppression and phase detection in PLLs, efficiency enhancement and harmonic suppression of the transmitter, power optimization and analog baseband design of the receiver. Through circuit- and system-level innovations, a Bluetooth Low Energy (BLE) transceiver supporting ultra-low-voltage operation at 0.5 V was realized, with the design and testing of four chips including PLLs, transmitters, and full transceivers.To address the problem of quantization noise suppression in fractional-N PLLs under low voltage, this work proposes an injection-locked phase-domain filter with an embedded FIR filter, which effectively suppresses quantization noise without requiring nonlinear calibration. The filter only relies on digital circuits and a ring-based injection-locked oscillator, making it suitable for low-voltage operation. Its functionality was validated with a BBPLL fabricated in 65 nm CMOS. Measurement results show that this method improves in-band phase noise and out-of-band fractional spurs by 25 dB and 10 dB, respectively.To address the difficulties in phase detection and quantization noise suppression in low-voltage fractional-N PLLs, two structures are proposed: a time-interleaved flip-flop phase detector (TI-FFPD) and a voltage-mode phase interpolator (VPI). The TI-FFPD achieves high linearity and low reference spur by using duty-cycle-based phase detection and common-mode ripple cancellation. The VPI, composed primarily of passive components, performs voltage-domain phase interpolation with excellent linearity, low power, and low noise. Fabricated in 28nm CMOS, the hybrid fractional-N PLL operates at 0.5V supply with only 0.78mW and achieves 0.61ps RMS jitter and ?59.4dBc fractional spur.For efficiency and performance optimization of the transmitter under low voltage, this work proposes an RDAC-based open-loop voltage control to eliminate common-mode ripple and improve reference spur of the hybrid PLL at low reference frequencies. A switching current-source oscillator with a shared bias resistor is introduced to optimize oscillator’s noise and power. Additionally, a duty-cycle control method for class-E/F2 power amplifiers is proposed to effectively suppress third-harmonic distortion. Fabricated in 65nm CMOS, the transmitter achieves 25.1% efficiency at 0.6V supply and 0dBm output power, satisfying BLE requirements.To reduce power consumption of the receiver under low voltage, a delay-based 1-bit demodulation architecture is proposed for efficient and simple GFSK demodulation. To address insufficient voltage headroom for analog baseband circuits at low voltage, a two-stage voltage-mode OTA with dual common-mode feedback loops is introduced, providing sufficient gain and stability without bias currents. A complete BLE transceiver was implemented in 28 nm CMOS, supporting 0.5 V operation and meeting BLE specifications, with the receiver consuming only 1.5 mW.In conclusion, this dissertation focuses on the design of PLLs, transmitters, and receivers under low voltage, advancing step by step from circuit- to system-level innovations. It proposes circuit blocks and system architectures suitable for low-voltage operation, which effectively reduce power consumption and improve system efficiency, contributing to overcoming the bottlenecks for low-voltage transceiver design.