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面向边缘智能场景的类脑多任务计算芯片及系统研究

A Brain-Inspired Multi-Tasking Computing Chip and System for Edge Intelligence

作者:马松辰
  • 学号
    2019******
  • 学位
    博士
  • 电子邮箱
    msc******.cn
  • 答辩日期
    2024.05.19
  • 导师
    施路平
  • 学科名
    仪器科学与技术
  • 页码
    147
  • 保密级别
    公开
  • 培养单位
    013 精仪系
  • 中文关键词
    类脑计算;芯片及系统;多任务处理;边缘计算;智能应用
  • 英文关键词
    Brain-Inspired Computing;Chips and Systems;Multi-Task Processing;Edge Computing;Intelligent Applications

摘要

类脑计算是借鉴脑科学基本原理发展的新型计算技术,是国际半导体协会推荐的后摩尔时代两个最有前途的新技术之一。快速发展的边缘智能对芯片的多任务处理能力提出了更高要求,但是边缘场景的资源限制使得现有计算平台难以满足低功耗、低延时地并行处理多个神经网络的性能要求。类脑计算芯片以其去中心化、事件触发、存算一体的架构特性,在能效、并行性和可扩展性展现了显著优势。然而,现有芯片在资源分配和任务调度方面尚缺乏灵活性,无法有效应对多任务带来的通用性、灵活性和高性能的综合挑战。针对以上问题,本文致力于发展一款面向边缘智能场景的类脑多任务计算芯片,提出了一套“负载分析—架构模型—芯片设计—应用验证”的系统性的研发思路,主要研究内容和成果包括:(1)针对当前研究缺乏对神经网络多任务负载的建模分析,本文结合边缘场景的部署需求,基于排队网络理论建模了具有不同拓扑结构的多智能任务负载和执行过程,并分析了现有芯片的多任务处理性能瓶颈来源。提出了类脑时空弹性智程执行模型和多级同异步混合并行计算模型,克服了类脑芯片在资源分配和任务调度所面临的灵活性挑战,实现了多任务运行隔离、负载均衡和灵活调度;(2)基于所提出的架构模型,研制了一款智能多任务类脑计算芯片TianjicX。提出了一种基于粗粒度异构融合原语指令集的功能核架构,实现了控制流与数据流的融合,并提升了时空执行的灵活性,解决了现有芯片可编程性差、任务执行灵活性差的难题;提出了多源异步触发的两级芯片时序机制,既实现了灵活的空间分组和执行环境隔离,又使边缘设备集成的外部数据源直接调控芯片时序信号的产生,让芯片中的功能核能够基于事件触发地执行任务,提高了芯片的利用率;(3)基于所研发的TianjicX芯片,搭建了一个边缘嵌入式类脑多任务处理计算平台,并开发了智能机器人。为提高智能体在开放世界场景处理复杂任务的能力,提出了多模态类脑算法和多任务类脑架构协同设计的思路。针对现有机器人位置识别系统的鲁棒性差、硬件处理效率低等挑战,提出了一种类脑多模态混合神经网络,实现了多模态、多尺度传感信息的编码和融合,充分发挥了类脑计算芯片在多任务并行处理方面的优势,使机器人能够鲁棒且高效地识别自然环境中的位置。本文为发展类脑通用计算系统、类脑通用具身智能提供了可借鉴的设计思路。

Brain-inspired computing is a novel computing technology developed based on the fundamental principles of brain science and is one of the two most promising new technologies recommended by International Roadmap for Devices and Systems for the post-Moore era. The rapid development of edge intelligence has placed higher and higher demands on the multi-task processing capability of chips. However, the resource constraints of edge scenarios make it difficult for existing computing platforms to meet the performance requirements of low power consumption, low latency, and parallel processing of multiple neural networks. Brain-inspired computing chips, with their features of decentralized many-core, event-driven, and collocated memory and computation architecture, demonstrate significant advantages in energy efficiency and parallelism. However, existing chips lack flexibility in resource allocation and task scheduling, making them ineffective in addressing the comprehensive challenges of generality, flexibility, and high performance posed by multi-tasking. To address these issues, this paper focuses on developing a brain-inspired multi-task computing chip for edge intelligence scenarios, proposing a systematic development approach of ``workload analysis - architecture model - chip design - application verification". The main research contents and contributions include: (i) Current research still lacks modeling and analysis for neural network multi-task loads. Therefore, based on queuing network theory and fully considering the load characteristics and deployment requirements of edge scenarios, we construct models of multi-intelligent task loads and execution processes with different topological structures in this paper. We also conduct an in-depth analysis of the performance bottlenecks of existing chips in processing multiple tasks. We propose ``Rivulet", a spatiotemporal elastic intelligent execution model, and ``HASP", a multi-level synchronous-asynchronous hybrid parallel computing model, overcoming the flexibility challenges faced by brain-inspired computing chips in resource allocation and task scheduling. These models can provide isolated processing environments for each task while supporting flexible sapatiotemporal resource‘s scheduling, facilitating load balancing and real-time performance of multi-tasking. (ii) Based on the proposed Rivulet execution model and HASP parallel computing model, a brain-inspired computing chip TianjicX for multi-intelligent-tasking is developed. A functional core architecture based on coarse-grained hybrid primitive instruction set is proposed, which achieves an efficient fusion of control flow and data flow, enhances the flexibility of spatiotemporal execution, and solves the problem of poor programmability and task execution flexibility in existing chips. Meanwhile, a two-level chip timing mechanism based on multiple asynchronous triggers is proposed, which not only realizes flexible spatial grouping and execution environment isolation, but also enables external data sources integrated into edge devices to directly regulate the generation of chip timing signals. This allows functional cores in the chip to execute tasks in an event-driven manner, thereby improving the chip‘s utilization efficiency. (iii) Based on the developed TianjicX chip, an edge-embedded brain-inspired multi-tasking computing platform is constructed, and intelligent robots are developed. To enhance the ability of intelligent agents to handle complex tasks in open-world scenarios, a collaborative design approach of multi-modal brain-inspired algorithms and brain-inspired multi-tasking architecture is proposed. To address challenges such as poor robustness and low processing efficiency of existing robots‘ place recognition systems, a brain-inspired multi-modal hybrid neural network model is proposed. This model achieves the encoding and fusion of multi-modal, multi-scale, and multi-dimensional sensory information, fully leveraging the advantages of brain-inspired computing chips in multi-task parallel processing. As a result, the robot is able to robustly and efficiently recognize places in natural environments. This paper opens a path for the development of general purpose brain-inspired computing systems and brain-inspired general embodied intelligence.