近年来随着智能手机、数字电视以及汽车音响等产品的迅猛发展，数字音频芯片市场增长强劲。由于人耳能分辨的声强范围达到135-140 dB，对微弱的噪声和失真十分敏感，所以精度是数字音频编解码芯片（Audio Encoder and Decoder）的关键指标之一。数模转换器（Digital-to-Analog Converter，DAC）作为音频编解码芯片的核心模块之一，一般需要16 bits以上的精度以保证较高的音质；目前随着技术进步，24 bits的高精度音频DAC也开始被大量使用。 本论文基于CMOS 40 nm工艺研究设计高精度音频ΔΣ DAC，包括数字ΔΣ调制器、数据加权平均（Data-Weighted Averaging，DWA）模块、4 bits开关电容DAC和模拟低通滤波器，对数字和模拟模块分别按照半定制和全定制集成电路设计流程进行电路设计，并完成了模拟电路的版图绘制和流片工作。在数字ΔΣ调制器设计中，提出了一个256倍过采样率（Over Sampling Ratio，OSR）下的三阶混合结构调制器，利用总线分割技术结合级间耦合稳定多级级联（Sturdy Multi-stage noise-ShAping，SMASH）ΔΣ调制器结构，节约15%硬件消耗的同时输出有效位数（Effective Number Of Bits，ENOB）提高了1.3 bits。数字部分的仿真和综合结果表明，在1.2 V电压和12.288 MHz频率下，数字ΔΣ调制器达到了23.24 bits精度，面积约1577.2 um2，功耗约164.5 uW。 模拟电路部分中，开关电容DAC在传统直接电荷转移结构基础上改进了电荷阵列充放电形式，同时集成了DWA模块以消除其单位电容失配带来的非线性；其模拟输出再经过一个多反馈低通滤波器进行滤波。仿真结果表明，模拟电路在20 KHz信号带宽下有效位数达到了19.22 bits，消耗了约9.5 mW功耗，流片的模拟核心电路面积约为0.261 mm2。测试结果表明，该ΔΣ DAC整体实现了86.3 dB信号噪声比，有效位数达到了14.04 bits。

In recent years, with the rapid development of smart phones, digital TVs, car audio and other products, the digital audio chip market has grown strongly. Since the sound intensity range that the human ear can distinguish reaches 135-140 dB and is very sensitive to weak noise and distortion, accuracy is one of the key indicators of digital audio codec chips. As one of the core modules of the audio codec chip, the Digital-to-Analog Converter (DAC) generally requires a precision of more than 16 bits to ensure high sound quality; currently, with the advancement of technology, the high precision of 24 bits Audio DACs have also begun to be used extensively. This paper studies and designs a high-precision audio ΔΣ DAC based on the 40 nm CMOS process, including a digital ΔΣ modulator, a data-weighted averaging (DWA) module, a 4-bits switched capacitor DAC and an analog low-pass filter. The digital and analog modules were designed according to the semi-customized and fully customized integrated circuit design processes respectively, and the layout drawing and tape-out of the analog circuits were completed. In the design of digital ΔΣ modulator, a third-order hybrid structure modulator at 256 times oversampling rate (OSR) is proposed, using bus division technology combined with inter-stage coupling to stabilize multi-stage cascade (Sturdy Multi-stage noise-ShAping, SMASH) ΔΣ The modulator structure saves 15% of hardware consumption while increasing the output effective number of bits (ENOB) by 1.3 bits. The simulation and synthesis results of the digital part show that at 1.2 V voltage and 12.288 MHz operating frequency, The digital ΔΣ modulator reaches an ENOB of 23.24 bits, an area of about 1577.2 um2, and a power consumption of about 164.5 uW. In the analog circuit part, the switched capacitor DAC improves the charge and discharge form of the charge array based on the traditional direct charge transfer structure, and integrates a DWA module to eliminate the nonlinearity caused by its unit capacitance mismatch; its analog output then goes through a multi-feedback Low pass filter for filtering. The simulation results show that the analog circuit has an effective number of 19.22 bits under a 20 kHz signal bandwidth, consumes about 9.5 mW power, and the tape-out analog core circuit area is about 0.261 mm2. The test results show that the ΔΣ DAC achieves an overall signal-to-noise ratio of 86.3 dB, and the effective number of bits reaches 14.04 bits.