锁相环作为一种主要的频率综合器架构，在通信系统、数据转换和电子仪器等领域中都发挥着不可或缺的作用。随着第五代移动通信技术（The Fifth Generation Mobile Communication，5G）和无线网络通信技术往高频率、大带宽、高吞吐等方向发展，锁相环作为信号链路的重要组成部分，在频率覆盖范围、相位噪声、功耗和锁定时间等方面都面临着巨大的挑战。本文主要围绕应用于 5G 通信和 Wi-Fi 6E 的宽带、低时钟抖动的快速锁定锁相环进行研究。 为了扩展锁相环的输出频率范围，实现向后兼容，本文设计了一个基于并联“8”字形电感和正向体偏置技术的差分Colpitts压控振荡器。通过电感的模式切换和三次谐波的叠加，该振荡器在实现宽输出频率范围的同时，能满足低相位噪声和低功耗的需求。同时在振荡器的输出增加了基于双模分频器的频率扩展模块，该分频器采用真单相时钟结构，可在二分频和三分频之间切换，最高工作频率可达24 GHz，动态功耗为75 uW/GHz。 针对传统电荷泵锁相环相位噪声和功耗较大的问题，本文采用亚采样锁相环架构，通过采样的方式优化了带内噪声源的噪声传递函数，打破了带内相位噪声和功耗之间的权衡。为了实现分数分频，本文还设计了一款高线性度的数字时间转换器来先验地延时参考信号。数字时间转换器采用开关电容的方式来改变延时，并通过重定时技术和互补结构提高了线性度、减少了输出噪声和分数杂散。针对数字时间转换器在工艺、电压和温度的变化下增益波动的问题，采用了最小均方算法进行后台校准。仿真结果表明，该数字时间转换器的积分非线性小于1.2个最低有效位。 考虑到本课题对锁定时间的需求，在采用辅助锁频环技术的基础上，本文提出了基于相位感知的动态电流补偿鉴频鉴相器电路。通过采样电路计数周期滑移，通过时间数字转化器量化输入信号间相位差的极性和大小，根据采样和量化结果针对性地改变电荷泵的电流，动态调整锁相环的环路带宽，缩短了系统的锁定时间。在锁相环锁定以后，关闭辅助锁频环，优化了锁相环的噪声和功耗。 在 65 nm 互补金属氧化物半导体工艺上完成了亚采样锁相环版图设计和流片，芯片面积为2.28 mm^2。仿真和测试结果表明，在1 V 电源电压下，锁相环可覆盖1.0 ~7.7 GHz 的频率范围，锁定时间为2.5 us，整体时钟抖动为188.7 fs，功耗为8 mW。

Phase-locked loops (PLLs), as a principal frequency synthesis, play an indispensable role in communication systems, data conversion, and electronic instrumentation. With the advancement towards higher frequency, wider bandwidths, and greater throughput in Fifth Generation Mobile Communication (5G) and wireless network communications, PLLs, as a critical component of the signal chain, encounter significant challenges in terms of frequency coverage, phase noise, power consumption, and locking time. This thesis primarily investigates wideband, low jitter, and fast-locking PLLs applied in 5G communications and Wi-Fi 6E. This thesis designs a differential Colpitts voltage-controlled oscillator based on a parallel "8" shaped inductor and the forward body biasing technique, extending the output frequency range of the PLL and achieving backward compatibility. Through the mode switching of the inductor and the superposition of the third harmonic, this oscillator meets the requirements of a wide frequency tuning range, low phase noise, and low power consumption. Furthermore, a frequency extension module based on a dual-mode divider is added to the oscillator‘s output, employing a true single-phase clock structure capable of switching between divide-by-two and divide-by-three, with a maximum operating frequency of 24 GHz and a dynamic power consumption of 75 uW/GHz. This thesis adopts a sub-sampling PLL architecture, optimizing the noise transfer function of in-band noise sources through sub-sampling. This approach breaks the trade-off between in-band phase noise and power consumption, addressing the primary issue in traditional charge pump PLLs. Additionally, the thesis designs a high-linearity digital-to-time converter (DTC) for the sub-sampling PLL, which can priorly delay the reference signal accroding to the division ratio, achieving fractional division. The DTC uses switched capacitors to change the delay, improving linearity and reducing output noise and fractional spurs through retiming technology and a complementary structure. To address the gain variation of the DTC due to changes in process, voltage, and temperature, a Least Mean Square (LMS) algorithm is employed for background calibration. Simulation result shows that the integrated non-linearity of this DTC is less than 1.2 Least Significant Bits (LSBs). This thesis also proposes a phase-aware dynamic current compensation phase frequency detector. Based on an auxiliary frequency-locked loop, the detector alters the current of the charge pump, by counting the cycle slips through a sampling circuit and quantifying the polarity and magnitude of the phase difference between input signals through a time-to-digital converter. So that, it can dynamically adjust the loop bandwidth of the PLL, shortening the system‘s locking time. After the PLL locks, the auxiliary frequency lock loop is turned off automatically, optimizing the PLL‘s noise and power consumption. The layout implementation of the sub-sampling PLL has been completed and taped out with 65 nm complementary metal oxide semiconductor process. The total chip area is 2.28 mm^2. Simulation and measurement results indicate that, operating at a 1 V power supply voltage, the sub-sampling PLL can cover a frequency range of 1.0 to 7.7 GHz, with a locking time of 2.5 us, a rms jitter of 188.7 fs, and a power consumption of 8 mW.