近年来，人工智能、大数据分析、云计算等新兴前沿技术的发展，在促进动态随机存取存储器（Dynamic Random Access Memory, DRAM）向高带宽发展的同时，DRAM作为现代电子设备中不可或缺的内存组件，其性能的提升也在加速计算性能的进步。DRAM 与这些计算技术之间形成了互助共生的关系，作为计算系统中不可分割的合作伙伴，它们互相促进，推动了彼此的持续发展。然而，目前DRAM工艺尺寸的进一步微缩，导致晶体管截止电流增大而带来了刷新频率接近极限的挑战，以及冯诺依曼架构下CPU与内存之间发展不均衡带来的的内存墙和功耗墙问题，都在一定程度上制约了系统性能的进一步提升，这些问题需要通过技术创新和架构优化来解决。本文提出了一种基于n-IGZO与p-LTPS（低温多晶硅）异质集成、以2T0C为架构、基于数字域可进行NAND计算的DRAM存内计算电路，并最终验证了方案的可行性。本文首先根据工艺厂商提供的IGZO晶体管转移特性与输出特性曲线建立并优化了基于Hspice的level 61模型，接着结合IGZO晶体管截止电流低、LTPS晶体管驱动能力强的特点，设计了n-IGZO与p-LTPS结合的2T0C架构存储单元以及数字域NAND计算单元的架构，并在此模型下仿真得到10秒量级的数据保持时间。此外，本文还针对2T0C的架构设计了对应的反馈环路、行列解码驱动电路以及灵敏放大器：反馈环路保证在有着严重耦合的情况下数据仍可正确读出以及存储节点内数据稳定性；行列解码驱动电路中分别采用了多层次译码、双轨电压以及树形译码器的策略，在有效减少晶体管使用数量的同时还兼顾了延时与功耗；在灵敏放大器的设计中根据工艺变化采用了不同电平的置位操作最终保证了电路的正常工作。本章最终搭建了64Kb规模大小的阵列电路，并对其进行了写读算操作的功能性仿真，仿真结果表明本文设计的存内计算电路可正确完成上述操作，并且对于工艺变化还具有一定的鲁棒性。
In recent years, the development of cutting-edge technologies such as artificial intelligence, big data analysis, and cloud computing has promoted the development of dynamic random access memory (DRAM) to high bandwidth. The improvement of DRAM is also accelerating the progress of computing performance. As inseparable partners in computing systems, they promote each other‘s continued development. The current further shrinkage of DRAM process size has led to an increase in transistor cut-off current, which has brought about the challenge of the refresh frequency approaching the limit, as well as the memory wall and power consumption wall caused by the uneven development between CPU and memory under the von Neumann architecture. All of them restrict the further improvement of system performance to a certain extent. These problems need to be solved through technological innovation and architectural optimization.This article proposes a DRAM in-memory computing circuit based on the heterogeneous integration of n-IGZO and p-LTPS (low temperature polysilicon), using 2T0C as the architecture, and capable of NAND calculations based on the digital domain, and finally verified the feasibility of the solution.This article first establishes and optimizes a level 61 model based on Hspice based on the measured data of IGZO transistors provided by the process manufacturer. Then, it designs the architecture of the memory unit and NAND computing unit that combines n-IGZO and p-LTPS, and simulates it under this model to obtain 10 Second-level data retention time. In addition, this article also designs corresponding feedback loops, row-column decoding drive circuits and sensitive amplifiers for the 2T0C architecture: the feedback loop ensures that data can still be read correctly even in the presence of severe coupling; The row and column decoding driver circuit adopts the strategies of multi-level decoding, dual-rail voltage and tree decoder respectively, which effectively reduces the number of transistors while also taking into account delay and power consumption; In the design of the sensitive amplifier, different levels of setting operations are used according to different processes to ensure the normal operation of the circuit. This article finally builds a 64Kb scale array circuit and performs functional simulation on it. The simulation results show that the in-memory computing circuit designed in this article can correctly complete the reading, writing and calculation operations, and also has a certain degree of robustness.
