人工智能的飞速发展对计算系统的数据处理能力提出了挑战，而传统芯片的算力发展面临着摩尔定律的减速和冯·诺依曼体系结构的瓶颈问题。单片三维集成（M3D）技术是一种新兴的半导体制造技术，有望解决上述问题，提高芯片集成度和算力。实现后道工艺兼容的器件制备是M3D技术的主要难点，国际上采用了碳纳米管、氧化物半导体、忆阻器等新兴材料与器件来实现。然而，当前基于碳纳米管晶体管和忆阻器的单片三维集成工艺研究还存在许多关键挑战。为此，本文开展了基于碳纳米管晶体管和忆阻器的后道兼容集成工艺研究，探索了器件级、阵列级和包含后道CMOS电路的全功能阵列的M3D方法并制备了原型样品，验证了所设计结构的系统级功能。本文取得的主要创新性成果如下：1. 针对器件级M3D工艺，本文研究了碳纳米管晶体管和忆阻器的后道兼容异质集成工艺，解决了后道金属图形化和高开关比忆阻器制备等关键工艺问题，研制了包含三个异质器件层的原型样品，从下到上依次集成了硅基MOSFET、模拟型忆阻器、基于碳纳米管晶体管和高开关比忆阻器的1T1R单元。基于该M3D集成工艺，本文设计了适合单样本学习任务推理的新型三维架构，结合器件测试和架构仿真的结果，该三维架构展示了与GPU相当的准确率，同时功耗降低为1/162。2. 针对阵列级M3D工艺，本文解决了碳纳米管晶体管钝化后性能下降等关键集成工艺问题，研究并探索了基于碳纳米管晶体管/高开比忆阻器2T2R单元阵列的三态内容寻址存储器的制造与集成方法，研制了一个具有三个阵列层的原型样品，从下到上依次为硅基控制逻辑、存内计算阵列、三态内容寻址存储器阵列及片上缓存阵列。本文进一步提出了三维混合存储器架构，在单样本学习计算任务中，所提的三维架构相对于二维芯片速度提升2.73倍，验证了三维集成工艺的优势。3. 围绕包含外围电路全可单片三维堆叠的忆阻器阵列工艺，本文通过搭建全自动在片测试系统解决了工艺研发过程中的多样品快速测试问题，实现了工艺与测试的迭代优化，克服了碳纳米管晶体管一致性、良率和阈值电压等难题，研制了大规模的后道兼容CMOS电路用于忆阻器阵列的外围电路。本文成功制造了包含2646个碳纳米管晶体管和1024个忆阻器的全可单片三维堆叠忆阻器阵列，并实现了其在忆阻器存内计算芯片顶层的堆叠，从垂直方向提高了忆阻器芯片的集成度。

The rapid development of artificial intelligence poses challenges to the data processing capabilities of computing systems, while the performance improvement of traditional two-dimensional chips is hindered by the slowdown of Moore's Law and bottlenecks in the von Neumann architecture. Monolithic three-dimensional (M3D) integration technology is an emerging semiconductor manufacturing technology that promises to resolve these issues and enhance chip integration and performance. Achieving back-end-of-line (BEOL) compatible device fabrication poses a significant challenge for M3D technology. To address this challenge, emerging materials and devices such as carbon nanotubes, oxide semiconductors, and memristors have been utilized. However, current research on M3D using carbon nanotube field-effect transistors and memristors still faces numerous key technical challenges. To address these chanllenges, this paper conducts research on BEOL compatible integration technology based on carbon nanotube field-effect transistors and memristors, exploring M3D methods at the device level, array level, and fully-functional array level where BEOL compatible CMOS is used as peripheral circuits. Prototype samples were fabricated to verify the system-level functionality of the designed structures. The main innovative achievements of this work are as follows:1. For device-level M3D integration, this paper investigates the BEOL compatible heterogeneous integration technology of carbon nanotube field-effect transistors and memristors, addressing key technological issues such as metal patterning in BEOL and the fabrication of memristors with a high on/off ratio. An M3D prototype sample containing three layers of heterogeneous devices was fabricated, integrating silicon-based MOSFETs, analog memristors, and 1T1R units based on carbon nanotube field-effect transistors and memristors with a high on/off ratio from bottom to top. Based on this M3D integration technology, a novel 3D architecture suitable for one-shot learning task inference was designed. According to device testing and architecture simulation results, this 3D architecture demonstrated GPU-equivalent accuracy while reducing power consumption to 1/162. 2. For array-level M3D technology, this paper resolved key integration issues such as performance degradation after passivation of carbon nanotube field-effect transistors. Manufacturing and integration methods for a ternary content-addressable memory array based on 2T2R units of carbon nanotube field-effect transistors and memristors with a high on/off ratio were researched and explored. A prototype sample with three array layers was fabricated, including silicon-based control logic, computing-in-memory arrays, ternary content-addressable memory arrays and on-chip buffer arrays from bottom to top. Moreover, a M3D hybrid memory architecture was proposed. In one-shot learning tasks, the proposed 3D architecture achieved a 2.73 times speed-up compared to a 2D baseline chip, demonstrating the advantage of 3D integration technology. 3. Regarding the technology of a fully-functional 3D stackable memristor array including peripheral circuits, this paper addressed the rapid testing problem of multiple samples during technology development by establishing a fully automatic on-chip testing system, realizing iterative optimization of technology and testing. Challenges such as the consistency, yield, and threshold voltage of carbon nanotube field-effect transistors were overcome, and large-scale BEOL compatible CMOS circuits for peripheral circuits of the memristor array were developed. A fully functional 3D stackable memristor array containing 2646 carbon nanotube transistors and 1024 memristors was successfully manufactured, and its vertical stacking on the top layer of the memristor computing-in-memory chip was achieved, significantly improving the vertical integration of the memristor chip.