近年来物联网技术飞速发展，万物互联的时代已经到来，为满足物联网设备对多种通信协议，特别是 WiFi 和蓝牙的支持需求，多模集成的射频收发机正逐渐取代传统的单模射频收发机。在多模收发机里，功率放大器（简称“功放”）是一个非常关键的环节，其线性度指标尤为重要。本文旨在提出一种集成在射频收发机中能够支持 WiFi/蓝牙双模并具有高线性度的功率放大器系统设计方案。本文提出的 WiFi/蓝牙双模功率放大器系统设计主要包含三大核心部分：电路失真分析、系统架构设计以及电路设计。首先电路失真分析聚焦于线性度指标，对电路进行失真建模分析以及针对性的优化。其次系统架构确立了整体的集成框架与高效的多模式切换机制。最终在此基础上，完成系统架构中的电路设计，从而实现了功率放大器的各项功能。本文针对这三部分分别进行了探索与研究。在电路失真分析上，本文对功率放大器电路的交调失真进行了深入研究与建模，提出了多栅晶体管技术和基于包络注入的自适应偏置电路结合的优化方式。通过分析这两种技术在降低交调失真方面的作用机理，总结了它们各自的优点与局限性。理论上，这两种技术的结合能够在大信号条件下实现优势互补。经过电路仿真验证，在 20 dBm 的输出功率下，结合后的优化电路相较于初始电路，IMD3优化了 9 dB，与单一优化电路相比，也有 4 dB 的优化。 在系统架构设计上，本文提出了一种复用 Balun 和驱动级的两路功放架构，够在较小的芯片面积上实现 WiFi 和蓝牙双模输出，同时保持出色的线性度性能。此外本文还设计了单刀三掷开关结构，以实现射频收发机中发射与接收的模式切换，并优化了相应的匹配网络电路设计。 在电路设计上，本文完成了功放系统中的所有必要电路模块设计，包括匹配网络、驱动级功放、输出级功放、偏置电路和片上电感等。这些设计共同实现了系统的增益控制、双模输出功能以及在射频收发机上的集成。 本文的功率放大器系统采用 22 nm CMOS 工艺设计，并集成在一套射频收发机上，后仿结果表明，在蓝牙模式下该系统能够达到 16 dBm 的饱和输出功率以及12.1% 功率附加效率，在 WiFi 模式下则能实现 24.3 dBm 的 1 dB 压缩点以及 25.5%的功率附加效率和 38.8 dB 的功率增益。此外，在输出功率为 20 dBm 时，该系统的 IMD3 指标低于-32 dBc，展现了良好的线性度性能。

In recent years, the technology of the Internet of Things (IoT) has developed rapidly, and the era of internet of everything has arrived. To meet the support needs of IoT devices for various communication protocols, especially WiFi and Bluetooth, multi-mode integrated radio frequency transceivers are gradually replacing traditional single-mode radio frequency transceivers. In multi-mode transceivers, the power amplifier (PA) is a very critical link, and its linearity is particularly important. This thesis aims to propose a design scheme for a power amplifier system integrated in the radio frequency transceiver that can support dual-mode WiFi/Bluetooth and has high linearity. The design of the proposed WiFi/Bluetooth dual-mode power amplifier system mainly includes three core parts: circuit distortion analysis, system architecture design, and circuit design. First, the circuit distortion analysis focuses on the linearity indicator, conducting distortion modeling analysis and targeted optimization of the circuit. Second, the system architecture establishes the overall integration framework and an efficient multi-mode switching mechanism. Finally, based on this foundation, the circuit design in the system architecture is completed, thus realizing the various functions of the power amplifier. This thesis has explored and researched these three parts separately. In terms of circuit distortion analysis, this thesis has conducted in-depth research and modeling on the intermodulation distortion of the power amplifier circuit, proposing an optimization method combining multiple-gated transistor technology and envelope signal injection based adaptive bias circuit. By analyzing the mechanisms of these two technologies in reducing intermodulation distortion, their respective advantages and limitations are summarized. Theoretically, the combination of these two technologies can achieve complementary advantages under large signal conditions. After circuit simulation verification, at an output power of 20 dBm, the optimized circuit combined has improved IMD3 by 9 dB compared to the initial circuit, and by 4 dB compared to the single optimization circuit. In terms of system architecture design, this thesis proposes a two-path power amplifier architecture that reuses Balun and driver power amplifier, capable of realizing dualmode output for WiFi and Bluetooth in a smaller chip area while maintaining excellent linearity performance. Additionally, a triple-throw switch (SP3T) structure was designed to achieve mode switching between transmission and reception in the radio frequency transceiver, and the corresponding matching network circuit design was optimized. In terms of circuit design, this thesis has completed the design of all necessary circuit modules in the power amplifier system, including matching network, driver power amplifier, output stage power amplifier, bias circuit, and on-chip inductance. These designs collectively realize the system’s gain control, dual-mode output function, and integration on the radio frequency transceiver. The power amplifier system in this thesis is designed using a 22 nm CMOS process and integrated into a set of radio frequency transceivers. Post-simulation results show that in Bluetooth mode, the system can achieve a saturated output power of 16 dBm and a power added efficiency of 12.1%, while in WiFi mode, it can achieve a 1 dB compression point of 24.3 dBm, a power added efficiency of 25.5%, and a power gain of 38.8 dB. Moreover, at an output power of 20 dBm, the system’s IMD3 indicator is below -32 dBc, demonstrating good linearity performance.