当今时代，信息爆炸正在发生，每年产生的数据越来越多，人工智能、生成式大模型等新内容需要更多的存储空间。存储器是保存和处理这些大数据的关键组件，因此存储器的开发和迭代变得愈发重要。 在内存领域，静态随机存储器的快速生成有SRAM Copmiler来支持。业界目前已经有成熟的SRAM Compiler来供开发人员使用，开发人员可在设计整个芯片的过程中使用SRAM Compiler来快速生成满足实际需求的SRAM内存阵列。但对于多次可编程存储器和其他非易失性存储器，由于其具有较多的模拟电路部分和复杂的整体结构，目前还没有相应的编译器。 课题组内开发的清华电子设计平台，一个模拟电路全流程自动化设计平台，为模拟电路的设计提供了一种类似软件开发的设计方法，支持用户使用Python语言来实现模拟电路的敏捷化开发。TED为模拟电路设计带来便利的同时也给非易失性存储器编译器的实现提供了可能性。本文基于TED平台提出了一种参数化和可跨工艺的非易失性存储器编译器的设计方案，并以MTP存储器为样例进行研究，完成了外围电路编译器的设计，对编译器实现过程中遇到的问题提出了一些创新的解决方案，并在S180BCD和S90BCD两种工艺下完成了验证。 本文的实验样例，MTP编译器有丰富的参数可供用户选择，用户可选择输入地址位宽来确定MTP的存储容量，选择输入输出数据位宽来确定MTP的输入输出结构，两者共同决定了MTP的整体结构。除此之外，用户还可以指定工艺。当参数和工艺确定之后，编译器就可以自动完成电路和版图的生成，在设计生成之后还会进行自动化测试和验证。其实现结果可供使用者根据不同的需求快速生成不同容量的MTP电路和版图，对工艺节点的迁移具有较强的自适应性，极大缩短了MTP存储器的开发周期以及减少了人工的投入。经测试验证，生成的MTP在三种工作模式下均能正常工作，并在两种工艺下均通过版图和原理图一致性检查。 本文以MTP编译器的实现为样例，提出了一套基于TED平台的非易失性存储器编译器的通用解决方案，展示了MTP编译器的实现成果，对非易失性存储器编译器的关键技术方案进行探索的同时，完善了TED平台的功能，为TED增加了一些在电路描述、总线布局和自动布线等方面之前未曾考虑到的问题的解决方案。
In today’s era, the information explosion is happening, more and more data is generated every year, and new content such as artificial intelligence and generative large models need more storage space. Memory is a key component in holding and processing this big data, so the development and iteration of memory becomes increasingly important.In the Memory domain, the rapid generation of Static Random-Access Memory （SRAM） is supported by SRAM Compiler. At present, the industry has mature SRAM Compiler for developers to use, developers can use the SRAM Compiler in the design of the whole chip process to quickly generate SRAM memory array to meet the actual needs. However, for Multiple-Time Programmable （MTP） and other non-volatile memory, due to its more analog circuit parts and complex overall structure, there is no corresponding compiler.The Tsinghua Electronic Design （TED） platform developed in the research group is an automatic design platform for the whole process of analog circuits, which provides a design method similar to software development for the design of analog circuits, and supports users to use Python language to realize the agile development of analog circuits. TED not only brings convenience to analog circuit design, but also provides the possibility to implement nonvolatile memory compilers. Based on the TED platform, this paper proposes a design scheme of parametric and cross-process non-volatile memory compiler, and takes MTP memory as an example to complete the design of the peripheral circuit compiler, and puts forward some innovative solutions to the problems encountered in the implementation of the compiler. The verification was completed under two processes, S180BCD and S90BCD.In the experimental example of this paper, the MTP compiler has a wealth of parameters for users to choose, users can choose the input address bit width to determine the storage capacity of MTP, choose the input and output data bit width to determine the input and output structure of MTP, both of which jointly determine the overall structure of MTP. In addition, the user can specify the process. When the parameters and process are determined, the compiler can automatically complete the generation of the circuit and layout, and after the design is generated, automated testing and verification will be carried out. The result can be used to quickly generate MTP circuits and layouts of different capacities according to different needs, and has strong adaptability to process node migration, greatly shortening the development cycle of MTP memory and reducing manual investment. It is verified that the generated MTP can work normally under the three working modes, and pass the Layout Versus Schematics （LVS） under both processes.Taking the implementation of MTP compiler as an example, this paper puts forward a set of general solution of non-volatile memory compiler based on TED platform, shows the implementation results of MTP compiler, explores the key technical solutions of non-volatile memory compiler, and improves the functions of TED platform. Adding solutions to TED’s previously unconsidered problems in circuit description, bus layout, and automatic routing.
