随着现代信息技术爆炸性的发展，SerDes技术作为一种设备与设备间高速且高效的有线传输方式受到了广泛的研究和应用。无论是学术界还是工业界，都将其视为一种研究热点向着能耗更低和速度更高的方向展开激烈的竞争和追逐。本文深入研究了SerDes技术的基本架构和关键技术，并基于此设计了一款面向JESD204C协议的串口收发机芯片。 本文首先对SerDes技术的基本原理和涉及的理论基础进行了介绍，随之介绍和分析了当下SerDes技术中的关键技术与设计难点，主要包括各种均衡技术和时钟数据恢复环路等。然后本文结合JESD204C协议确定了所设计的SerDes收发机的整体架构与设计指标，并针对其所涉及的技术难点进行了讨论并提出了合理的解决方案。比如采用T型线圈解决输出节点带宽不足的问题，采用投机型反馈解决DFE反馈时序约束紧张的问题，采用SS-LMS算法解决DFE抽头系数自适应的问题，采用两倍过采样的CDR结构来解决时钟速度带来的瓶颈问题等。另外本文还在Simulink中对SerDes收发机的结构和其包含的数模混合环路进行了建模和仿真，以验证方案的可行性。 本文在28nm CMOS工艺下完成了SerDes收发机的电路设计，并针对发射机中的FFE电路和输出驱动器，接收机中的CTLE电路和Slicer电路以及时钟产生电路的设计进行了详细的分析和仿真结果的验证。仿真结果表明，本设计的SerDes能实现预期的功能和性能指标，并具有一定的性能裕量。 本文还完成了芯片的版图设计并交付流片，最终对回片进行了测试。测试结果表明，本芯片的工作的数据率范围为312Mbps-32Gbps，可同时支持JESD204C和JESD204B两种模式，能够在最高速度32Gbps下在14.9dB的测试信道上实现低于1e-12的误码率，并仍有0.5UI的时序裕度。本芯片面积为1.4mm2，在32Gbps下总共消耗203mW的功耗，其中发射机50mW，接收机153mW，最终的能效为6.3pJ/bit。同时本芯片所设计的DFE抽头系数自适应环路和时钟数据恢复环路均工作正常，系数和相位能够快速且准确的收敛。
With the explosive development of emerging information technology, SerDes has been widely studied and applied as a high-speed and efficient wireline transmission manner between devices. Both academia and industry regard it as a research hotspot, engaging in fierce competition and pursuit towards lower energy consumption and higher speed. This thesis delves into the basic architecture and key technologies of SerDes, and based on this, designs a wireline transceiver for the JESD204C protocol. This thesis first introduces the basic principles and theoretical foundations of SerDes, and then introduces and analyzes the key technologies and design difficulties in current SerDes, mainly including various equalization techniques and clock data recovery. Then, this thesis combines the JESD204C protocol to determine the overall architecture and performance of the designed SerDes, and discusses the technical difficulties involved and proposes reasonable solutions. For example, using T-shaped coils to solve the problem of insufficient output node bandwidth, using speculative feedback to solve the problem of tight DFE feedback timing constraints, using SS-LMS algorithm to solve the problem of adaptive DFE tap coefficients, and using a CDR structure with 2X oversampling to breakthrough the bottleneck caused by clock speed. In addition, this thesis also modeled and simulated the structure of the SerDes and its included analog and digital hybrid loop in Simulink to verify the feasibility of the scheme. This thesis completes the circuit design of the SerDes transceiver under the 28nm CMOS process, and provides detailed analysis and simulation results for the FFE and output driver in the transmitter, CTLE and Slicer in the receiver, and clock generation circuit. The simulation results show that the SerDes designed in this thesis can achieve the expected functions and performance, and has a certain performance margin. This thesis also completed the layout design of the chip and tape-out, finally tested the chip. The test results show that the operating data rate range of this chip is 312Mbps-32Gbps, and it can support both JESD204C and JESD204B protocol. It can achieve an BER below 1e-12 on a test channel of 14.9dB at a maximum speed of 32Gbps，and still has timing margin of 0.5UI. This chip has an area of 1.4mm2 and consumes a total power of 203mW at 32Gbps, with a transmitter of 50mW and a receiver of 153mW. The final power efficiency is 6.3pJ/bit. At the same time, the DFE tap coefficient adaptive loop and clock data recovery loop designed by this chip are working normally, and the coefficients and phases can converge quickly and accurately.
