随着集成电路的发展器件尺寸进入纳米时代后，各种新型器件结构相继被提出，无结型环栅场效应晶体管（JL-GAAFET）因其具有良好的短沟道效应以及低热预算成为了下一个技术节点的备选器件结构。而随着晶体管尺寸的不断减小，本征涨落的影响越来越大，严重限制着器件进一步发展。本文以JL-GAAFET为载体，探究了本征涨落效应对其性能的影响，并针对其应用展开研究。 首先，本论文研究了本征涨落中功函数涨落（WFV）以及线边粗糙涨落（LER）对JL-GAAFET性能的影响。对于WFV影响来讲晶粒尺寸对器件Vth的影响占主导。研究发现晶粒尺寸越小，对器件性能的影响越小。比较了WFV对两种主流结构NanoSheet与NanoWire性能的影响。其中NanoWire由于结构优势在DIBL与SS等小尺寸效应的均值上占优势，并且阈值电压受涨落的影响更小。另外比较了LER与WFV涨落对器件性能的影响程度，发现整体来讲LER的影响更大。并且证明了AFM中KPFM模块是测量功函数的有效手段。为下一技术节点的器件结构的选择与开发提供了有力指导。 其次，针对JL-GAAFET的栅极材料进行优化，通过产生偶极子的方式调制栅极的有效功函数来满足JL-GAAFET的应用。并且通过分析发现，偶极子是由于氧离子向Al层中扩散，在HfO2层中留下了氧空位而形成的。并且可通过调节Al层的厚度来调节有效功函数来满足未来低功耗或高性能器件的需求。 最后，针对基于JL-GAAFET的1T1C DRAM单元出发，优化DRAM单元的性能，提出2T1C结构优化DRAM的保持特性，提高保持时间，存“1”状态的保持时间可达625ms。此外针对浮体效应对2T1C存“0”状态的轻微恶化现象，提出DT+双功函数(DMG)结构进行优化。通过降低空穴隧穿宽度，以及降低空穴存在的有效沟道长度有效的减缓了浮体效应的影响。最终可达DRAM单元在存“1”是的保持时间为291ms，存“0”状态时的保持时间为490ms。为未来3D DRAM提供有力方向。
As integrated circuits device size scaling in the nanometer era, a variety of new device structures have been proposed in which Junctionless Gate All Around Field Effect Transistor (JL-GAAFET) has become one of the most promising alternative device for the next technology node owing to its good short-channel effect and low thermal budget. With the size scaling down, the impact of intrinsic rise and fall is increasing extremely, imposing great limitation to further development. In this paper, the effects of intrinsic rise and fall on the performance of JL-GAAFET are comprehensively investigated and the applications of JL-GAAFET are demonstrated subsequently. First, we focus on the influence of line-edge roughness (LER) and work-function variation (WFV) on the properties of JL-GAAFET. It is found that the effect of grain size on device performance is positively correlated with grain size. From the perspective of WFV, grain size exerts a dominant effect on Vth. Comparing the effect of WFV on two mainstream structures, Nanosheet and Nanowire, we discover that nanowire performs better in DIBL and SS due to its structural advantage, and the threshold voltage is less affected by variation. We also compare the influence of LER and WFV on device performance and find that LER has more influence on JL-GAAFET . In addition, it is verified that the KPFM module in AFM is an effective mean to measure the work function. It provides a strong guidance for the selection and development of the device structure for the next technical node. Next, in order to meet the application, the material component of the gate in JL-GAAFET is optimized by modulating the effective work function of the gate as a result of dipole generation. We consider that the dipole is formed because of the diffusion of oxygen ions into the Al layer and resultant generation of oxygen vacancies in the HfO2 layer. Besides, the effective work function could be tuned by adjusting the thickness of Al layer for low-power and high-performance application. . Finally, we propose a 2T1C structure to optimize the performance of DRAM cells based on JL-GAAFET to achieve a retention time of 625ms for the storage "1" state. Furthermore, to address the slight deterioration of the "0" state in 2T1C structure due to the floating body effect, 2T+Double Work Function (DMG) structure is proposed to obtain reduction of hole tunneling width and channel length where holes exist, decreasing the floating body effect effectively. In addition, a DRAM cell with a retention time of 291ms in the "1" state and 490ms in the "0" state is realized providing an emerging direction for future 3D DRAM.
