随着5G通信，人工智能和高性能计算等行业和应用的迅猛发展，待处理和待传输的数据量正经历“爆炸式”增长，不断对有线通信系统的带宽等性能提出新要求。高速串行接口作为解决带宽需求的关键技术，被广泛应用于通信网络、嵌入式系统以及各种消费类电子产品当中。本文对高速串行接口发射机中的关键技术展开了以下研究： 详细分析了一种基于电感峰化的高速CMOS时钟分布方法，该方法可以扩展分布网络的带宽，滤除高频段的噪声，从而加快CMOS时钟的转换沿，并减小输出抖动。提出了一种内部节点受控的单位脉冲产生器（INCC-1UIPG）,可产生高质量的高速单位脉冲，提供给高速CML串化器使用。所提出的INCC-1UIPG利用了动态逻辑，减少堆叠，电荷控制等技术，相比于已有结构，具有速度快、码间串扰小、对时钟负载轻、输出抖动小的优点。针对超高速发射机中合路节点时序窗口窄，且难以在PVT下收敛的问题，设计了一种基于相位插值器的后台时序校准环路。该校准环路能够迫使合路节点处的时序收敛进入指定相位附近1LSB以内，并跟随PVT的变化。本文对环路的整个收敛过程进行了电路级仿真，并最终在芯片测试中验证了其效果。基于以上研究成果，在65nm CMOS工艺下，设计了一款1/4速率时钟架构的PAM-4发射机，完成了架构选取-电路设计-版图绘制-后仿迭代-芯片测试的完整流程。发射机在后仿真中实现了128Gb/s的PAM-4数据率，具有321.1mW的总功耗和2.5pJ/bit的能量效率，可以均衡约10dB的信道衰减。最后，搭建芯片测试平台对发射机芯片进行了测试。经测试验证，发射机芯片能够以较高的质量输出最高32GHz的时钟码型和最高64Gb/s的8周期NRZ码型，并且利用PRBS7码型实现了90Gb/s的PAM-4数据率。
With the rapid development of industries and applications such as 5G communication, artificial intelligence, and high-performance computing, the amount of data to be processed and transmitted is experiencing an "explosive" growth, constantly posing new challenges for the bandwidth and other performance of wireline communication systems. As the key technology to solve the bandwidth requirement, high-speed serial interface is widely used in communication networks, embedded systems, and various consumer electronics. This article conducts the following research on key technologies in high-speed serial interface transmitters:A high-speed CMOS clock distribution network based on inductive peaking was analyzed in detail. This method can expand the bandwidth of the distribution network, filter out high-frequency noise, accelerate the conversion edge of the CMOS clock, as well as reduce the output jitter.An internal-node-charge-controlled unit interval pulse generator (INCC-1UIPG) has been proposed, which can generate high-quality 1UI pulses for use in high-speed CML serializers. The proposed INCC-1UIPG utilizes dynamic logic, stack reduction, charge control, and other technologies. Compared to existing structures, it has the advantages of faster speed, lower inter symbol interference, lighter clocking load, and lower output jitter.A background timing calibration loop based on phase interpolator is designed to address the narrow timing window and the poor convergence under PVT of combining nodes in ultra-high-speed transmitters. This calibration loop can force the timing closure at the combining node to enter within 1LSB near the specified phase, and automatically track the variation of PVT. This article conducted circuit level simulation of the entire convergence process of the loop and ultimately verified its effectiveness in chip testing.Based on the above research results, a 1/4 rate clock architecture PAM-4 transmitter was designed under 65nm CMOS process, fulfilling the complete process of architecture selection, circuit design, layout drawing, post simulation iteration, and chip testing. The transmitter achieved a PAM-4 data rate of 128Gb/s in post simulation, with a total power consumption of 321.1mW and an energy efficiency of 2.5pJ/bit, which can equalize the channel attenuation of about 10dB.Finally, a chip testing platform was built to test the transmitter chip. After verification, the transmitter chip can deliver clock pattern up to 32GHz, 8-cycle NRZ pattern up to 64Gb/s with high quality, and achieves a PAM-4 data rate of 90Gb/s using PRBS7 pattern.
