随着工艺特征尺寸不断缩小，工艺浮动对电路质量的影响愈发严重，由此引发的良率问题制约了产业的进一步发展。在流片前的设计阶段加入良率分析流程可以有效降低工艺浮动的影响，功率、性能、面积和良率（Performance, Power, Area, and Yield，PPAY）一体化设计度量标准正逐步取代原有的功率、性能和面积标准，成为电子设计自动化发展的重要方向。但是目前的良率分析存在着仿真次数多、速度慢等问题，设计人员面临着昂贵的迭代设计。在基于良率的的自动优化中，受限于优化方向不明确，这些问题表现得更为明显。 基于这一背景，本文提出了一套完整的良率分析与优化解决方案。针对当前仿真次数多、速度慢的核心问题，从仿真运算、算法提升、建立新型器件模型三个层级开展研究工作。仿真层级，算法的基础工具灵敏度分析通过重用传递链实现加速；算法层级，采用灵敏度分析和确定性算法直接加速良率分析与优化流程；模型层级，提出了一种快速建模方法，以适配新型器件的良率分析。 仿真运算层级中，灵敏度分析可以为良率提供寻找最优值的方向信息，提升效率。但在与N个时间点状态相关的目标函数中，其计算复杂度高达O(N^2)。本文提出了一种加速方法，通过重用反向传递过程，将点链结构转变为网状结构，将计算复杂度降低到O(N)。 算法提升层级中，本文从3-Sigma（罕见失效事件）和High-Sigma（极其罕见失效事件）切入，分别开展针对性研究。High-Sigma良率中，提出了一种快速灵敏度重要性采样良率分析方法，基于灵敏度下降算法寻找最优均值偏移向量，建立局部替代模型二次采样；并进一步提出了全灵敏度对抗重要性采样良率优化方法，避免了外部优化器中的采样过程。3-Sigma良率中，电路性能表征更为复杂，我们提出了快速蒙特卡罗良率分析方法，基于灵敏度和正交基采样快速建模；并进一步提出了差分进化的全局优化与灵敏度下降的局部优化相结合的良率优化方法，加快算法收敛。经实验验证，所提方法在保证高精度前提下，均有明显的速度提升。 器件模型层级中，新材料、新器件蓬勃发展，对器件建模提出了成本低、周期短的新要求。为了适应新型器件良率分析要求，本文采用分母分子拟合算法对器件建立行为级模型，基于物理知识划分更精细的电容模型，并将其应用于良率分析中，进一步从器件模型角度探究加速基于良率的电路设计流程。

With aggressive technology scaling, the impact of process variation on the circuit quality is becoming more and more important. The yield problem caused by process variation has restricted the further development of the industry. Adding yield analysis in the circuit design stage before tape-out can effectively reduce its impact. The integrated design metrics of Power, Performance, Area, and Yield (PPAY) are gradually replacing the original Power, Performance, and Area (PPA) standard, which has become an important direction for the development of Electronic Design Automation (EDA). However, the current yield analysis mostly needs many simulations and costs a lot of time, and designers have to face expensive iterative designs. In yield-based automatic optimization, these problems are more obvious due to the constraints of ambiguous optimization directions. Based on this background, this paper proposed a complete yield analysis and optimization solution. The research work was carried out at three levels: simulation acceleration, algorithm improvement, and new device modeling to solve the core problems of a high number of simulations and slow speed. At the simulation level, sensitivity analysis, the basic tool of the yield algorithms, can be accelerated by reusing the transmission chain; at the algorithm level, a yield analysis and optimization acceleration method based on sensitivity analysis and deterministic algorithms was proposed; at the device model level, a rapid modeling method was proposed to adapt to the yield analysis of new devices. At the simulation level, sensitivity analysis can provide direct information for finding the optimal value in yield analysis and optimization to improve efficiency. However, when the objective function is related to the state of N time points, its computational complexity is as high as O(N^2). An acceleration method to transform the point-chain structure into a mesh structure by reusing the transfer chain was proposed, which reduces the computational complexity to O(N). At the algorithm level, we conducted targeted research in 3-Sigma (rare failure events) and High-Sigma (very rare failure events) circuits. In the High-Sigma circuit, a Fast Sensitivity Importance Sampling (FSIS) yield analysis method was proposed, where the Optimal Mean Shift Vector (OMSV) is found based on the sensitivity-descent algorithm, and a local surrogate model is built for the second sampling process. An All Sensitivity Adversarial Importance Sampling (ASAIS) yield optimization method was further proposed, which avoids the sampling process in the outer optimizer. In the 3-Sigma circuit, the circuit performance characterization is more complicated. We proposed a Fast Monte Carlo (FMC) yield analysis method, based on sensitivity and Orthogonal Sampling to quickly build the model. We further proposed a method that combines the global optimization algorithm (Differential Evolution) and the local optimization algorithm (sensitivity-descent) to accelerate the algorithm convergence. The proposed methods have been verified in experiments and had a significant speed increase while ensuring high accuracy. At the device model level, new materials and new devices are in the ascendant, and new requirements for low cost and short cycle are put forward for device modeling. In order to meet the requirements of the new device yield analysis, we used the Denominator Numerator Fitting algorithm to build a behavioral device model, and divided the capacitance model based on physical knowledge. The model was applied to the yield analysis, and further explored the acceleration of the yield-based circuit design from the perspective of the device model.