随着通信标准的不断演变，通信码率和功耗要求不断提高，其中的模数转换器（ADC）逐渐成为整个系统的性能瓶颈。相比于其他类型ADC，连续时间（CT）Delta- Sigma ADC以其高能效、易驱动的阻性输入以及自带的抗混叠滤波特性等优势被广泛应用于无线通信终端系统中。随着CMOS工艺更新，数字电路的工作速度和功耗不断改善，而模拟电路则面临着信号电压空间变小、放大器增益和线性度变差和器件参数受工艺、电压和温度影响变大的挑战。本论文在40nm CMOS工艺利用数字算法辅助模拟电路设计的方法，研究设计了一个用于5G通信接收机的50MHz带宽12bit精度带数字校准的连续时间Delta-Sigma ADC。采用自顶向下设计流程，首先对Delta-Sigma ADC进行行为级建模与仿真，通过系统级结构对比和参数扫描，选定2-2 级联、16倍过采样率和3bit量化的电路结构。本论文提出了一种针对多比特反馈数模转换器的多环路数字校准方法，消除其静态失配及动态误差。此外还设计验证了基于最小均方差的数字噪声消除滤波器的后台校准模块，缓解ADC中模拟运算放大器的性能要求，从而降低功耗。在晶体管级电路设计中，运放采用基于反相器的两级前馈补偿结构以实现较高能效。ADC第一级选取前馈结构实现2阶噪声整形，可直接从第二个积分器输出提取第一级量化噪声以驱动第二级电路。同时对ADC数字校准算法的Verilog代码进行了功能验证及FPGA原型验证，最后对ADC模拟电路和数字校准模块进行了混合信号仿真验证。仿真结果显示，2阶单环Delta-Sigma调制器在各种环境下有效精度均能大于9.8bit；在tt 27℃环境下带数字前台校准的4阶两级级联Delta-Sigma ADC可以达到84.9dB和81.5dB的SNR和SNDR，模拟电路功耗为29.7mW。本论文还介绍了一个基于40nm CMOS工艺的10MHz带宽12bit精度单环连续时间Delta-Sigma ADC的版图设计及测试工作，该ADC测试结果有效精度为9.53bit，相较后仿真结果下降约1.5bit。两个工作的目标有效精度相同，相比较单环Delta-Sigma ADC，级联结构可以维持环路稳定性的同时增加噪声整形的阶数，从而降低过采样率，在需要更高带宽的高速应用中更具优势。
Continuous evolution of communication sets more stringent requirements on bit rate and power consumption of standards, and analog-to-digital converter (ADC) is gradually becoming performance bottleneck of the whole system. Compared with other ADC architecture, continuous-ime (CT) delta-sigma ADC is widely used in wireless communication terminals, due to its good power efficiency, advantages such as accuracy, easy-driven resistive input and intrinsic anti-aliasing filtering. With CMOS technology scaling, digital circuits benefit a lot in operation speed and power consumption; while analog circuits face challenges such as smaller signal headroom voltage, worse amaplifier gain and linearity, and larger process voltage and temperature variations. With methodology of digital algorithm-assisted analog circuit design, a 50MHz-bandwidth 12bit-accuracy continuous-time delta-sigma ADC in 40nm CMOS for 5G receiver application are studied and designed in this thesis. Based on top bottom design flow, behavior-level modeling and simulation of delta-sigma ADC are conducted first; an ADC structure of 2-2 MASH, ×16 oversampling rate and 3bit quantization are selected by system-level optimization and parameter sweep. A multi-loop calibration method for multi-bit feedback DAC is proposed in this thesis to mitigate its static mismatch and dynamic error. In addition, this paper also verifies a least-mean-square-based digital calibration block of noise cancellation filter has been designed and verified to relax performance requirements of ADC operational amplifiers and save power consumption. In the transistor-level design, an inverter-based two-stage feedforward-compensated amplifier is adopted to achieve high energy efficiency. The 1st stage of the ADC utilizes feedforward structure to realize 2nd-order noise shaping, in this way, quantization noise of the 1st stage is directly extracted from output of 2nd integrator to drives the 2nd stage circuit. Meanwhile, Verilog code of ADC digital calibration algorithm has been functionally verified and FPGA prototype verification has been carried out. Finally, mixed-signal simulation and verification including ADC analog circuit and digital calibration block have been performed.Simulation results shows that effective number of bits (ENOB) of the 2nd-order single loop delta-sigma modulator is larger than 9.8bit at different corners. At tt 27℃ corner, the SNR and SNDR of the 2-2 MASH delta-sigma ADC with digital foreground calibration are 84.9dB and 81.5dB, respectively; and the power consumption of ADC analog circuit is 29.7mW. Layout and measurement work of a10MHz-bandwidth 12bit accuracy single loop continuous-time delta-sigma ADC in 40nm CMOS is also presents in this thesis. The measured ENOB of this ADC is 9.53bit, which is about 1.5bit lower than post-simulated one. The target effective number of bits of both work is the same. Compared with single loop delta-sigma ADC, MASH structure could increase the order of noise shaping and maintain loop stability simultaneously, leading to a reduced oversampling rate, and thus showing more merits in high-speed applications.
