模数转换器（ADC）是集成电路的关键模块之一。在经典的ADC架构中，流水线ADC因其同时具有高采样率和高精度，被广泛应用于无线收发、雷达系统、医疗影像等应用领域中。此外，时间交织（TI）架构通过复用多个ADC通道，能够实现更高的采样速度。然而实际电路中各种非理想因素使得ADC偏离理想传输特性，从而降低其性能指标。相比较无校准ADC方案，使用校准算法校准时间交织流水线ADC中非理想因素能够实现更小的面积和功耗。各种结构ADC及其校准算法是目前学术界中数模混合电路的研究热点之一。本论文调研并总结了近年国内外时间交织流水线ADC校准算法的主要研究现状和发展方向。建模分析了器件失配等非理想因素对ADC性能的影响，对主流数字校准方法进行了研究，基于28nm CMOS工艺为一个12bit 2GS/s时间交织流水线ADC设计了数字校准算法电路。为了消除芯片工艺、电压和温度带来的偏差，本论文采用多种数字后台校准消除该ADC的通道内级间增益误差和通道间失配误差。采用伪随机（PN）注入和最小均方(LMS)算法消除1.5bit级电路的增益误差；其中提出了一种低成本的PN注入方式，对输入信号幅度无限制，同时也不增加额外的比较器。采用移动平均(MMA)和LMS算法校准消除了通道间失调和增益失配。通过相关函数估计通道间采样时间失配，并分别采用模拟数控延时线电路或数字FIR滤波器进行补偿。模拟补偿方式只要求单调的数控延时线，对其精度和线性度的要求较低。数字域采样时间失配估计利用LMS算法实现除法，降低了校准模块的功耗和面积。本论文设计的ADC校准算法易于拓展到不同结构流水线ADC和不同通道数时间交织ADC。本论文完成了四通道 12bit 2GS/s 时间交织流水线ADC及其校准算法的行为级建模、校准相关模拟电路的晶体管级设计以及校准数字电路的专用集成电路（ASIC）设计。其中数字部分完成了功能仿真、现场可编程门阵列（FPGA）验证、数字后端版图设计和后仿工作。在28nm CMOS的仿真结果显示：在奈奎斯特输入频率下，本论文所设计的校准将2GS/s时间交织流水线ADC信号噪声失真比（SNDR）从46.2dB提高到61.1dB, 无杂散动态范围（SFDR）从49.6dB改善到74.1dB。数字校准模块面积仅为243um*242um，仅消耗28.2mW功率。
Analog-to-digital converter (ADC) is one of key blocks in integrated circuits; among classic ADC architectures, pipeline ADC is widely used in wireless transceivers, radar systems, medical imaging and other applications due to its capability of achieving high sampling rate and high resolution simultaneously. Furthermore, time-interleaving (TI) technique enables higher sampling speeds by multiplexing several ADC channels. However, various circuit nonidealities make ADC deviate from its ideal transfer characteristics, degrading its performance. Compared with ADC without calibration scheme, using calibration algorithm to mitigate circuit nonidealities of time-interleaving pipeline ADC could achieve smaller chip area and consumption. The of various ADC structures together with their calibration algorithm are popular in mixed-signal circuit research.In this thesis, the mainstream research and direction of TI pipeline ADC calibration algorithm in recent years are investigated and summarized. The effects of various circuit nonidealities (e.g. mismatch) on ADC performance are modelled and analyzed, and digital calibration circuits are designed in 28nm CMOS for a 12bit 2GS/s TI pipeline ADC. To remove variations caused by chip process, voltage and temperature, several digital background calibrations are applied to cancel inter-stage gain error of pipeline ADC and inter-channel mismatch of TI ADC. In this thesis, PN injection and least mean square (LMS) algorithm are used to calibrate gain error of 1.5bit stage circuit, here a low cost PN injection method is proposed, without limitation of input signal amplitude nor additional comparators. Both moving average (MMA) and LMS algorithms were adopted to eliminate inter-channel offset and gain mismatches. The inter-channel sampling time mismatch is estimated by a correlation function, which is further compensated by an analog digital-controlled delay line or a digital FIR filter. The analog compensation only requires monotonicity of digital-controlly delay line, and with low requirement on its accuracy and linearity. Digital division is implemented by LMS algorithm in estimation of sampling time mismatch, reducing power consumption and area of calibration block. The ADC calibration algorithms designed in this thesis can be applied to pipeline ADC with different structures and TI ADC with different number of channels.In this thesis, behavior modeling of a four-channel 12bit 2GS/s TI pipeline ADC and its calibration are completed, as well as relevant transistor level design of analog circuit for calibration, and ASIC circuit design of digital background calibration. The digital flow includes function simulation, FPGA verification, backend layout design and post simulation. Simulation results in 28nm CMOS show that with Nyquist input frequency, the proposed calibration technique improves the SNDR of the 2GS/s TI pipeline ADC from 46.2dB to 61.1dB, and its SFDR from 49.6dB to 74.1dB. The digital calibration block has an area of 243um*242um and consumes only 28.2mW power.
