随着自动驾驶、3D成像等技术的兴起，激光雷达已成为了业界关注的焦点，而高精度宽量程时间数字转换器（TDC）是激光雷达系统中的核心模块。在众多的TDC结构中，基于现场可编程门阵列（FPGA）的TDC具有开发周期短，成本低等优点；而基于专用集成电路（ASIC）的TDC具有线性度好，受PVT影响小等优点。论文首先调研总结了TDC国内外研究现状和主流发展方向，并确立了在FPGA采用抽头延迟线（TDL）结构实现多通道TDC的技术路线，分析该架构的技术难点，并最终采用Wave-union方法提升TDC的分辨率和测量精度。其中分别设计了基于加法树和子段分解原理的编码器，用于解决单边沿和多边沿信号在TDL中传输的气泡问题。本论文提出了两个改进：首先改进了深度为16的子段分解编码器，可有效解决TDL标定中的零bin宽问题；其次改进了一种校准bin宽的加权方法，很大程度上提升了TDC中bin宽标定的线性度，非常适用于现阶段激光雷达。论文基于ZYNQ7020开发板在300MHz系统时钟下设计实现了一个八通道TDC；其分辨率为8.31ps，通道间测量精度为30.79ps，测量范围大于10ms。为了进一步提高分辨率，本论文改进设计了三边沿TDC，该TDC在ZYNQ7020中分辨率和测量精度分别为5.64ps和50.51ps；在ZYNQ7100中其指标分别可达到3.76ps和8.00ps。本论文还在MATLAB中验证了改进的加权校准方法，校准后的TDC差分非线性（DNL）和积分非线性（INL）分别为(-0.22,0.30) 和(-0.21,0.82)LSB。本论文还基于40nm CMOS工艺完成了一个用于ASIC-TDC的低静态相位误差延迟锁定环（DLL）的晶体管级电路设计工作，在传统电荷泵上提出了改进，增加了电流补偿和匹配电路；前仿真结果表明，所设计DLL的静态相位误差在tt工艺角27oC下只有890.78fs，输出参考时钟抖动峰峰值为1.09ps，消耗5.24mW功耗。在此基础上初步完成了一个两级TDC电路的仿真验证，在4ns输入时间间隔下，该TDC的误差为-55ps。
With the rise of autonomous driving and 3D imaging technology, lidar has become one of the focuses of the industry, and high-precision and wide-range time-to-digital converter (TDC) is key block of lidar system. Among TDC structures, FPGA-TDC is known of short development cycle and low cost; while ASIC-TDC has good linearity and low performance variation over PVT.Firstly, domestic and international research and development have been investigated and summarized in this thesis, robust TDL structure has been selected to design multi-channel TDCs in FPGA, with its technique difficulties analyzed and Wave-union method applied to improve resolution and accuracy. Two encoders based on adder tree and subsegment decomposition are implemented, respectively, to solve the bubble problems due to single-edge and multi-edge signal transmissions in TDL. In this thesis, two improvements are proposed during design of FPGA-TDC: the first one is a subsegment decomposition encoder with a depth of 16, effectively solving the problem of zero width bin in TDL calibration; and the second one is a weighting method for bin width calibration, which improves the linearity of bin width calibration in TDC and is suitable for modern lidar design. An eight-channel TDC has been implemented in ZYNQ7020 with a system clock of 300MHz, with 8.31ps achieved resolution, 30.79ps measurement accuracy among channels and larger than 10ms measurement range. In order to enhence resolution, three-edge TDCs are also designed, which obtains a resolution of 5.64ps and a measurement accuracy of 50.51ps in ZYNQ7020, and these specifications are improved to 3.76ps and 8.00ps, respectively, in ZYNQ7100. The improved weighted calibration method is verified in MATLAB, the DNL and the INL of the calibrated TDC are (-0.22,0.30) and (-0.21,0.82) LSB, respectively. Moreover, transistor-level circuit design of a low static phase offset DLL has been completed in 40nm CMOS technology. In this thesis, the improvement of traditional charge pump is proposed, adding current compensation and current matching circuit. Simulation results show that at tt corner and temperature of 27oC, the static phase error of the designed DLL is only 890.78fs, the PtP output reference clock jitter is 1.09ps, and the power consumption is 5.24mW. Based on DLL design, preliminary simulation of a two-stage TDC has been conducted, and its simulated output error is -55ps, with an input time interval of 4ns.
