随着现代通信技术的发展，高速接收机要求其中的模数转换器（Analog-to-Digital Converter, ADC）满足中等（8~10bits）分辨率和数GS/s采样率的性能要求。由于无模拟放大器的结构，逐次逼近型（Successive Approximation Register, SAR）ADC在面积和能效方面优势明显；随着工艺更新和结构改进，其采样率也得到了极大的提升。多通道时域交织 （Time-Interleaved, TI） 技术能够突破工艺对速度的限制，进一步提高ADC采样率。时域交织SAR结构也是目前主流ADC研究的热点之一。本论文在28nm CMOS工艺提出设计了一个8bits 1GS/s单通道SAR ADC，并在此基础上研究设计一个8bits 8GS/s八通道时域交织SAR ADC，完成了ADC行为级优化、管级电路设计和部分版图绘制工作。单通道SAR ADC采用2-bit/step结构，由两个全差分电容型数模转换器（Capacitance Digital to Analog Converter, CDAC）、三个比较器和SAR逻辑组成；仅用四个比较周期就完成8bits量化，提高了ADC速率。为了降低比较器失调电压失配对多比较器ADC精度带来的影响，设计中加入了基于跨导调制的前台比较器失调校准，没有引入额外的功耗和延时。改进了其中分裂分段CDAC和定制SAR逻辑的设计，进一步优化ADC电路性能。仿真结果显示，该单通道SAR ADC在1GS/s采样率和奈奎斯特输入频率下，信号噪声失真比（Signal-to-Noise-Distortion Ratio, SNDR）和无杂散动态范围（Spurious-Free Dynamic Range, SFDR）分别为49.2dB和60.9dB，仅消耗1.4mW功耗，实现了5.9fJ/conv-step的能效（Figure-of-Merit, FoM）值。八通道时域交织SAR ADC的研究中，设计了高速时钟产生电路，并定制设计了基于传输门逻辑的高速数字多路选择器，降低了逻辑延时和硬件开销。针对2-bit/step SAR ADC中存在的负电压和共模电压偏移问题，改进设计了一个“先1bit再2bit”的SAR ADC结构，提高了八通道时域交织SAR ADC在多个PVT（Process, Voltage, Temperature，工艺角，电源电压，温度）条件下的精度，保证了电路的可靠性和稳定性。仿真结果显示，该八通道时域交织ADC在8GS/s采样率和奈奎斯特输入频率下，达到了47.2dB的SNDR和51.7dB的SFDR，总功耗为13.9mW，实现了9.3fJ/conv-step的FoM值。此外本论文还完成了10bits 200MS/s SAR ADC参考源电路的管级电路和版图设计工作以及该ADC的测试工作。
With development of modern communication technology, analog-to-digital converters (ADCs) with medium-resolution (8~10bits) and several GS/s sampling rate are required in high-speed receivers. Because of analog amplifier-free structure, successive approximation register (SAR) ADC is competitive on chip area and efficiency; with technology scaling and architecture innovation, its sampling rate is also boosted a lot. Multi-channel time-interleaved (TI) technique breaks limitation of technology on ADC speed, and increases ADC sampling rate further. Now TI SAR is one of the mainstream ADC research hotspots.An 8bits 1GS/s single-channel SAR ADC has been proposed and designed in 28nm CMOS in this thesis, including behavioral-level optimization, transistor-level circuit design and part of layout design; based on that, an 8bits 8GS/s 8-channel TI SAR ADC has been designed. The single-channel SAR ADC uses a 2-bit/step structure, which is composed of two fully differential CDACs, three comparators and a SAR logic. The 8bits quantization could be completed within only four comparison cycles, increasing ADC speed. In order to reduce performance degradation of ADCs with multiple comparators due to comparator offset mismatch, a foreground comparator offset calibration based on transconductance modulation is proposed without introducing additional power consumption or delay. A split segmented CDAC and a custom-designed SAR logic are also improved to further optimize ADC performance. Simulation results show that with 1GS/s sampling rate and Nyquist input frequency, SNDR and SFDR of the single-channel SAR ADC are 49.2 dB and SFDR, respectively, and the power consumption is only 1.4 mW, achieving a FoM of 5.9 fJ/conv-step.In the research of 8-channel TI SAR ADC, high-speed clock generation circuit and digital multiplexer based on transmission logic are designed to reduce gate delay and hardware overhead. To solve the problems of negative voltage and common mode voltage shift in 2-bit/step SAR ADC, a 1-then-2-bit/step ADC architecture is designed, improving accuracy of 8-channel TI SAR ADC under various PVT conditions, enhencing its reliability and stability. Simulation results demonstrate that with sampling rate of 8GS/s and Nyquist input frequency, the 8-channel TI ADC achieves an SNDR of 47.2dB and an SFDR of 51.7dB. Power consumption of the total ADC is only 13.9mW, resulting into an impressive FoM of 9.3fJ/conv-step. In addition, reference voltage circuit of a 10bits 200MS/s SAR ADC has been designed in this thesis, including circuit design, layout work; and measurement work of this SAR ADC has also been conducted.
