数模转换器(Digital to Analog Converter，DAC)是负责将数字信号转换为模拟信号的关键模块，是连接数字系统和真实世界的桥梁。随着信息时代的飞速发展，对数据速率要求的不断提升对作为通信系统核心器件的DAC提出了更高的要求，特别是在有线通信领域，超高速DAC已经成为限制系统性能提升的瓶颈所在。如何在维持DAC性能的同时实现采样率的大幅提升，是目前国内外众多学者、机构研究的焦点。正是基于这一研究背景，本文开展了下述各项工作：本文定位了超高速DAC研究的两项关键技术，多通道时间交织技术和多相时钟后台校正技术。多通道时间交织技术通过将多个单通道DAC输出进行组合，突破现有工艺的带宽限制，实现采样率的成倍提升。但在有效解决采样率不足这一问题的同时，超高速DAC采用时间交织技术也面临新的挑战，由于芯片制造工艺的限制，单通道DAC之间不可避免地存在偏差，导致频谱出现杂散分量，进而使得DAC动态性能恶化。其中，针对通道间时序失配，采用多相时钟后台校正技术能够实现持续跟踪和快速校正，解决多相时钟偏差所导致的交织杂散分量，有效解决采样率提升后DAC动态性能恶化这一问题。本文基于TSMC 28nm CMOS工艺设计了一颗8bit、32GS/s DAC芯片，首次采用了四通道非归零交织技术，设计了一种四相时钟延时调节电路，并进行流片验证。电路设计方面，本文选取了部分关键电路模块，介绍工作原理和设计过程中所考虑的因素。版图设计方面，本文介绍了芯片整体版图布局和设计原则，并对关键模块特别是时钟树、电流树等无源网络设计展开了详细说明。本文介绍了8bit、32GS/s DAC的仿真验证和芯片测试工作。由于芯片指标较高，为了确保芯片测试的功能和性能，本文在仿真验证阶段做了大量工作。本文搭建了平台用于DAC的整体前仿验证，仿真结果显示整个奈奎斯特频带内SFDR大于55dBc。后仿验证阶段，一方面对关键模块单独搭建平台进行验证，确保功能正常；另一方面进行DAC整体仿真，针对仿真资源和设计周期受限的问题，选取合适的寄生参数进行仿真验证，确保仿真精度的同时加快迭代速度。流片完成后，设计测试方案并开展芯片测试，目前芯片可以工作在16GS/s采样率下，在2.3GHz信号频率处SFDR大于60dBc，在5.4GHz信号频率处SFDR大于40dBc。
Digital to analog converter (DAC) is a key component for converting digital signals into analog signals, bridging digital systems and the real world. With the rapid development of the information age, the continuous improvement of data rate requirements has put forward higher requirements for DACs as the core devices of communication systems. Especially in the field of wired communication, ultra-high-speed DACs have become a bottleneck that limits the improvement of system performance. How to achieve a significant increase in sampling rate while maintaining DAC performance is the focus of research by many scholars and institutions at home and abroad. Based on this research background, the following works are carried out:This paper locates two key techniques for ultra-high-speed DAC research, multichannel time interleaving technology and multiphase clock background correction technology. Multichannel time interleaving multiplies the sampling rate by combining multiple single-channel DAC outputs to overcome the bandwidth limitations of existing processes. However, while effectively solving the problem of insufficient sampling rate, ultra-high-speed DACs also face new challenges in using time interleaving technology. Due to the limitations of the chip manufacturing process, there are inevitable deviations between single-channel DACs, resulting in spurious components in the spectrum, which in turn deteriorates the dynamic performance of the DAC. Among them, in view of the timing mismatch between channels, the multiphase clock background correction technology can be used to achieve continuous tracking and fast correction, solve the interleaved spurious components caused by the multiphase clock deviation, and effectively solve the problem of DAC dynamic performance deterioration after the sampling rate increases.In this paper, an 8-bit, 32GS/s DAC chip is designed based on TSMC 28nm CMOS process, with a four-phase clock delay adjustment circuit designing and four-channel non-return-to-zero time-interleaving technology for the first time, and tape-out verification is performed. In terms of circuit design, this article selects some key circuit components to introduce the working principle and the factors considered in the design process. In terms of layout design, this paper introduces the overall floorplan and design principles of the chip, and introduces the design of some components, especially passive networks such as clock trees in detail.This article describes the simulation verification and chip test of 8-bit、32GS/s DACs. Due to the high chip specifications, in order to ensure the function and performance of chip testing, this article has done a lot of work in the simulation verification stage. In this paper, a platform is built for the overall pre-simulation verification of DACs, and the simulation results show that the SFDR in the entire Nyquist band is greater than 55dBc. In the post-simulation verification stage, on the one hand, the key modules are verified by building a separate platform to ensure normal function; On the other hand, the overall simulation of DAC is carried out, and appropriate parasitic parameters are selected for simulation verification to ensure simulation accuracy and accelerate iteration speed for problem limited simulation resources and design cycle. At present, the chip can work at 16GS/s sampling rate, SFDR greater than 60dBc at 2.3GHz signal frequency, and SFDR greater than 40dBc at 5.4GHz signal frequency.
