三态内容寻址存储器（TCAM）是一种可高速、高并行操作的存内搜索引擎，广泛应用于数据搜索和过滤，例如路由 IP 查找等。相比传统的基于静态随机存取存储器（SRAM）的 TCAM，基于新型非易失性存储器（eNVM）的 TCAM 可具有更高的存储密度。在不同类型的 eNVM 中，阻变存储器（RRAM）表现出高速、低功耗、与先进 CMOS 技术的高度兼容性等优势，因此在实现下一代非易失性 TCAM 方面具有巨大潜力。然而，基于 RRAM 的 TCAM 在实际应用中仍存在不足，主要原因在于器件的非理想特性，例如高阻态（HRS）和低阻态（LRS）之间的电阻比（R-ratio）较小、HRS 单元的泄漏电流和读干扰等，这在很大程度上限制了其搜索速度和可靠性。在此背景下，本文提出了高可靠且可实现电流检测功能的匹配线感应方案，从而设计出高速、高可靠性且低能耗的 TCAM。本文的主要创新性工作包括：（1）针对RRAM器件的非理想因素对TCAM搜索可靠性的影响，本文提出了一种高可靠匹配线感应方案。该方案通过降低匹配线充电电压来避免对存储单元造成读干扰的影响，并通过隔离晶体管实现感应电压的全摆幅输出从而提高感应裕度。相较0.7V感应电压摆幅，本文采用的0.9V摆幅方案，可以实现28%的速度-可靠性均衡搜索性能指标的提升。（2）针对RRAM器件中使用阻态校验电路带来的额外面积开销，本文通过可调电容和计数器的搭配使用，使得匹配线感应方案兼具阻态校验的功能，从而避免了阻态校验电路的额外面积开销。（3）针对RRAM器件的弛豫效应对TCAM搜索可靠性的影响，本文提出一种针对器件编程层面的窄脉宽forming方法。实验数据证明该方法可以通过减小forming脉宽，降低电导漂移标准差和越界器件个数这两个指标，分别最高降低了52%和49%的实验结果，从而有效改善了RRAM器件的弛豫效应。本文设计了一种基于RRAM的高可靠TCAM，采用标准CMOS 28nm工艺库实现，存储容量为64字×32比特。通过仿真分析，验证了系统电路的功能，并对速度、能耗等指标进行了统计分析。仿真结果表明，电路搜索时长可以达到0.72 ns，匹配线能耗为0.56 fJ/bit/search，匹配线的能量延迟积为0.41 fJ?ns/bit/search。相较于其他方案，本文提出的TCAM方案具有更低的搜索延迟和更低的能量延时积。
The ternary content-addressable memory (TCAM) is a high-speed and highly parallel searchable memory used extensively for data search and filtering, such as routing IP lookups. Compared to the traditional TCAM based on static random-access memory (SRAM), TCAM based on emerging non-volatile memory (eNVM) can have higher storage density. Among different types of eNVM, resistive random-access memory (RRAM) exhibits advantages such as high speed, low power consumption, and high compatibility with advanced CMOS technology, making it a promising technology for implementing the next-generation non-volatile TCAM. However, RRAM-based TCAM still faces challenges in practical applications due to non-ideal device characteristics, such as small resistance ratio (R-ratio) between high-resistance state (HRS) and low-resistance state (LRS), leakage current of HRS cells, and read-disturbance, which significantly limit its search speed and reliability. In this context, this thesis proposes a high-reliability and currentdetection- enabled matching-line sensing scheme to design a high-speed, high-reliability, and low-power TCAM. The main innovative contributions of this thesis include: (1) To address the impact of non-ideal factors in RRAM devices on TCAM reliability, this thesis proposes a high-reliability matching-line sensing scheme. This scheme can ensure that the charging voltage of the matching line is lower than the reading voltage, thereby avoiding the interference of read disturbance on storage cells. In addition, this scheme provides a full swing output for the sensing voltage through isolation transistors, offering greater sensing margin.Compared to the 0.7V sensing voltage swing, the 0.9V swing scheme adopted in this thesis can achieve a 28% improvement in the speedreliability balanced search performance metric. (2) To address the additional area overhead caused by the resistance verification circuit in RRAM devices, this thesis combines the use of tunable capacitors and counters in the matching-line sensing scheme to achieve resistance state verification functionality, thereby avoiding the extra area overhead of resistance state verification circuits. (3) To address the impact of relaxation effects in RRAM devices on TCAM reliability, this thesis proposes a narrow-pulse forming method at the device programming level. Experimental data demonstrate that this method is shown to reduce the standard deviation and the number of out-of-bounds devices, effectively improving the relaxation effect of RRAM devices. The experimental results show that the proposed method can achieve a maximum reduction of 52% and 49% for these two metrics, respectively. This thesis presents a high-reliability TCAM based on RRAM, implemented using a standard CMOS 28nm process library with a storage capacity of 64 words x 32 bits. Through simulation analysis, the functionality of the system circuit was verified, and performance metrics such as speed and energy consumption were statistically analyzed. Simulation results show that the circuit search time can reach 0.72 ns, the energy consumption of the matching line is 0.56 fJ/bit/search, and the energy-delay product of the matching line is 0.41 fJ?ns/bit/search. Compared with other schemes, the TCAM proposed in this thesis has lower search latency and lower energy-delay product.
