半导体工艺及电子封装正在向微型化和高集成化快速发展，这使芯片功率密度不断攀升，同时增加了芯片高结温导致热失效的风险，也对热管理技术提出新的挑战。因而，通过以热阻分析和热阻优化为代表的热管理方式应对这一挑战是大势所趋。然而，目前缺乏针对芯片的热阻分析方式，无法明晰芯片内部各部分结构所引入热阻，更加难以开展针对性的热阻优化，这或将制约芯片的进一步发展。因此，为了解决芯片散热问题，提高其性能及服役寿命，提出热阻模型及优化方式具有重要意义。2022年以来，具有高功率、高集成、高散热需求的5G技术正迈向全面市场普及，这意味着更大的散热挑战。FC-BGA芯片是5G通信基站的核心功能部件及产热部件。因此，本文将FC-BGA芯片作为研究对象，从热阻分析的角度厘清芯片内部热阻大小及比例，明确芯片散热的薄弱环节，判定芯片热阻的优化空间，进而通过热设计优化热阻，以达到降低芯片结温、保障芯片安全运行和延长芯片服役寿命等目的。热阻分析的具体形式是使用热阻网络模型来描述芯片的散热路径及特性。传统的热阻只适用于一维情况，而对于三维封装芯片则需要考虑结构等因素引入的额外热阻。目前，双热阻模型、星形网络热阻模型等通过简化散热路径，可以用于芯片结温预测。然而，上述模型要么具有“总包性”，仅给出各散热路径的总热阻，不探究内部热阻分布；要么具有“拟合性”，通过数学手段拟合不同散热条件下预设的热阻网络，难以将结构和热阻对应起来。本文从芯片结构物性出发，使用扩展热阻对导热热阻进行补充，给出了详细热阻网络模型的定义方式，厘清了芯片中结壳热阻的组成及比例，并确定了具有重要长远价值和创新意义的芯片热源布局优化方向。进一步，详细讨论了芯片热源位置与结温之间的关系，提出其边角优势散热特点，并利用仿生优化方法对热源进行了重新布局，使芯片内部热阻下降12.09%。火积的概念在热阻分析及优化上已有大量应用，本文通过对芯片开展火积耗散热阻分析，讨论了适用于芯片的火积耗散特征温度及火积耗散热阻优势。将其与详细热阻网络模型进行对比，阐明了两者在总热阻、扩展热阻形式上的统一性和特征温度节点上的差异性，并进一步论证了火积理论在芯片热阻分析及热阻归因上的长处。
Semiconductor technology and electronic packaging technology are developing rapidly towards miniaturization and high integration, which makes the heat flux rise continuously, and increases the risk of thermal failure caused by high junction temperature. This phenomenon poses new challenges to thermal management technology. Therefore, it is an inevitable trend to deal with this challenge through thermal management represented by thermal resistance analysis and thermal resistance optimization. However, at present, there is no thermal resistance analysis method for the chip, and the thermal resistance of each part cannot be clearly defined. This makes it more difficult to carry out targeted thermal resistance optimization, which will restrict the further development of the chip. Therefore, in order to solve the heat dissipation problem of the chip and improve its performance and service life, it is of great significance to propose the thermal resistance model and optimization method. Since 2022, 5G technology with high power, high integration and high heat dissipation demand is moving towards full market penetration, which means greater heat dissipation challenges. FC-BGA chip is the core function and heat-generating component of 5G communication base station. Therefore, this paper takes FC-BGA chip as the research object. The size and proportion of the internal thermal resistance of the chip will be clarified from the perspective of thermal resistance analysis, and the weak link of chip heat dissipation will be clarified. Then, the optimization space of chip thermal resistance is evaluated, and the thermal resistance is optimized through thermal design to reduce the chip junction temperature, ensure the safe operation of the chip and extend the service life of the chip. The specific form of thermal resistance analysis is to use the thermal resistance network model to describe the heat dissipation path and characteristics. The traditional thermal resistance is only applicable to one-dimensional cases, while for three-dimensional packaging chips, the additional thermal resistance introduced by factors such as structure should be considered. At present, the two resistor model and the star network model can be used to predict the junction temperature by simplifying the heat dissipation path. However, the above models either give the total thermal resistance of each heat dissipation path, without exploring the internal thermal resistance distribution; Or it is "fitting", and it is difficult to match the structure and thermal resistance by fitting the preset thermal resistance network under different heat dissipation conditions by mathematical means. Based on the physical properties of the chip structure, the thermal spreading resistance is introduced to supplement the thermal conductance resistance. Thus, the detailed definition of the thermal resistance network model is given, the composition and proportion of the thermal resistance in the chip are clarified, and the optimization direction of the is also determined. Further, the relationship between the heat source location and junction temperature is discussed in detail, and its heat dissipation advantage at edge and corner positions are proposed. The heat source is rearranged using the bionic optimization method, which reduces the internal thermal resistance of the chip by 12.09%. The concept of entransy has been widely used in thermal resistance analysis and optimization. This paper discusses the characteristic temperature of entransy dissipation and the advantages of entransy based heat dissipation resistance by analyzing the entransy dissipation based thermal resistance. Compared with the detailed thermal resistance network model, it is uniform in the form of total thermal resistance and thermal spreading resistance, and different in the characteristic temperature nodes. Furthermore, the advantages of entransy theory in chip thermal resistance analysis and thermal resistance attribution are demonstrated.
