铁电存储器（FeRAM）是一种利用了铁电晶体的铁电效应的新兴的非易失存储器件，它具有长时间数据保持，高擦写次数，抗辐射等优良特性，在工业、汽车、物联网、医疗以及航空等领域都有不错的应用前景。铁电存储器相比其他的非易失存储器件，如带电可擦可编程只读存储器（EEPROM）和闪存（Flash memory），工作电压、平均功耗更低，读写时间更短。因此铁电存储器是非易失存储器市场具有较强竞争力的新型存储器件之一。本论文为了解决铁电存储器设计过程中的诸多关键问题，为了给高密度、低功耗、高速率的铁电存储器设计提供一定的基础，主要研究了铁电存储器中的单晶体管单铁电电容存储单元（1T1C）以及相应的阵列架构的设计方法。并结合了以铪锆氧(Hf0.5Zr0.5O2)为材料的铁电薄膜的测量数据，对铁电存储器的关键电路和外围电路进行了读写仿真、性能分析及电路优化。首先，在分析、采用现有铁电存储器阵列架构以及参考电压生成电路的基础上，我们利用H-SPICE电路仿真工具对铁电存储器中的阵列架构进行了仿真分析，确定了最小工作电压、工作频率、铁电薄膜额定面积以及灵敏放大器（SA）工作点等关键电路参数。在设计过程中，我们还对铁电电容的数学模型进行了改进，在不改变铁电电容模型计算精度的前提下，减少了该电容模型的计算量，进而使得仿真时间大幅减少。在铁电存储器关键电路设计、仿真的工作基础上，本文还提出了一种新型的用于铁电存储器架构中的电涌保护电路，该电路在能降低电涌电流，有效保护铁电存储器电路长期正常运行的同时，还能起到降低铁电存储器读写功耗的作用。我们完整地研究了规模为16kb的铁电存储器的设计方法，在存储单元以及阵列架构的设计研究基础上，确定了外围电路的基本结构、读写时序以及工作参数，并对其进行了仿真分析和一定的优化。
Ferroelectric random access memory is an emerging non-volatile memory device that utilizes the unique characteristic of ferroelectric material. Excellent characteristics such as long-term data retention, high erasing times, and radiation resistance result in the wide application of FeRAM in industries, automobiles, Internet of Things, medical and aviation fields. Compared with other non-volatile memory devices, such as EEPROM or Flash memory, FeRAM has obvious advantages in operating voltage, average power consumption, and read and write time. FeRAM is one of the emerging memory with strong competitiveness in the non-volatile memory market.In order to provide a basis for the design of high-density, low power consumption, and high-speed FeRAM, this paper mainly researches 1T1C storage unit in ferroelectric memory and the corresponding array architecture. Combined with the measurement data of ferroelectric material, the key circuits and peripheral circuits of the ferroelectric memory were simulated by H-SPICE to be analyzed and optimized.Based on the analysis of existing array architectures and reference voltage generation circuits in FeRAM, H-SPICE was used to simulate and analyze the array architecture in ferroelectric memory, and determine essential circuit parameters such as voltage, operating frequency, ferroelectric film rated area, and DC operating point of sense amplifier. During the design process, we also improved the mathematical model of the ferroelectric capacitor, and successfully reduced the calculation amount without changing the calculation accuracy of the ferroelectric capacitor model, thereby greatly reducing the simulation time.This paper also proposes a novel surge protection circuit that reduces the power consumption of reading and writing while effectively protecting the normal operation of the ferroelectric memory circuit.A 16kb ferroelectric memory was finally designed and simulated by this work. Based on the research and design of memory cell circuit and array architecture, basic structure of peripheral circuits, reading and writing scheme and other operating parameters were designed and optimized.
