在基于图形进行模拟电路设计的传统模式下，工艺、参数发生变化时需要重新进行电路设计，复用率极低，并且在此模式下需要资深工程师进行大量人工干预，因此小规模的模拟集成电路设计周期也非常长。借鉴于软件的敏捷开发模式，敏捷芯片设计通过高层次抽象、模块组件化、优化工具自动化，一方面降低了芯片设计的入门门槛，另一方面有机结合工程师的经验和优化算法，有望进一步发展版图自动化。TED（Tsinghua Electronic Design）是本课题组开发的支持跨工艺和参数化的敏捷芯片设计工具，它是一个混合信号电路开发框架，通过Python编程进行模拟电路设计，有助于促进电路模块的复用，提高模拟电路设计效率，从而减少模拟电路设计工程师的重复工作，最终达到降低芯片设计入门门槛、缩短产品开发周期的目的。然而，其目前仅支持手动布局，使电路模块在不同工艺下的布局结构相同，但是不同工艺、参数电路模块尺寸会发生变化进而导致生成不合理的布局，导致面积利用率低下。因此，本文基于TED平台研究实现模拟电路的自动布局以实现不同工艺、参数下依然能够生成紧凑、满足模拟电路设计约束的布局。本文主要通过结合模拟集成电路模块级和器件级自动布局以解决模拟电路中广泛使用的约束，如对称约束、公共质心匹配约束等。首先基于序列对表示方法实现了能够处理对称约束的模块级自动布局，并且支持在不同工艺、参数的条件下生成紧凑的布局。结合TED全流程自动化设计平台与晶体管自动布局，能够实现满足设计指标的运算放大器电路的自动布局，目前已应用于各种结构的运算放大器电路中；其次，本文实现了器件级布局，主要包括：（1）实现了晶体管单元阵列的共质心模式和堆积模式的自动布局算法，以适应不同电路需求；（2）实现了共质心模式的电容单元摆放和电容阵列的生成，并成功在一层金属上布线，且尽可能对称布线，满足了最小面积的需求；（3）实现了优化互连线长度的电阻单元阵列的自动布局算法，布线长度最高减少49.4%。整体而言，本文基于敏捷设计工具TED实现了跨工艺、参数化的模拟电路自动布局，提高了其版图设计自动化程度，在提高模拟集成电路设计效率上有广阔的应用前景。目前这项工作已应用于与多所高校的合作科研，并成功部署到某大型企业中。

In the traditional pattern of analog circuit design based on graphics, when the process and parameters change, the circuit design needs to be re designed, and the reuse rate is extremely low. Moreover, in this pattern, a large number of manual interventions by senior engineers are required, so the design cycle of small-scale analog integrated circuits is very long. In view of the agile development mode of software, agile chip design, through high-level abstraction, modularization and automation of optimization tools, reduces the entry threshold of chip design on the one hand, and organically combines the experience of engineers and optimization algorithms on the other, which is expected to further develop layout automation. TED (Tsinghua Electronic Design) is an agile chip design tool developed by our research group, which supports cross process and parameterization. It is a mixed signal circuit development framework. Analog circuit design through python programming helps promote the reuse of circuit modules, improve the efficiency of analog circuit design, reduce the repetitive work of analog circuit design engineers, and ultimately achieve the goal of reducing the entry threshold of chip design and shortening the product development cycle. However, at present, it only supports manual layout, so that the layout structure of circuit modules under different processes is the same, but the size of circuit modules under different processes and parameters will change, resulting in unreasonable layout and low area utilization. Therefore, based on the TED platform, this paper studies the automatic layout of analog circuits to achieve a compact layout that meets the constraints of analog circuit design under different processes and parameters.In this paper, the constraints widely used in analog circuits, such as symmetry constraints and common centroid matching constraints, are mainly solved by combining module level and device level automatic layout of analog integrated circuits. First, based on the sequence pair representation method, a module level automatic layout that can handle symmetry constraints is realized, and compact layouts can be generated under different processes and parameters. Combined with the TED whole process automation design platform and automatic transistor layout, it can realize the automatic layout of operational amplifier circuits that meet the design indicators. At present, it has been applied to operational amplifier circuits of various structures; Secondly, the device level layout is implemented in this paper, which mainly includes: (1) the automatic layout algorithm of common centroid mode and stacking mode of transistor cell array is implemented to meet different circuit requirements; (2) The placement of capacitor cells and the generation of capacitor arrays in the common centroid mode are realized, and the wiring is successfully arranged on one layer of metal, and the wiring is symmetrical as possible, meeting the requirement of minimum area; (3) The automatic placement algorithm of resistance cell array with optimized interconnect length is realized, and the maximum wiring length is reduced by 49.4%.On the whole, based on the agile design tool TED, this paper realizes cross process, parametric automatic layout of analog circuits, improves the automation of layout design, and has broad application prospects in improving the efficiency of analog integrated circuit design. At present, this work has been applied to cooperative scientific research with many universities and successfully deployed to a large enterprise.