高速SerDes技术凭借其接口数量少、信道串扰小以及高速长距离传输的高可靠性等优势被广泛应用于数据中心、服务器以及芯片之间的数据传输之中。而随着大数据时代下物联网、人工智能、云计算等新兴信息技术的迅速发展，系统之间海量的信息交互对数据的传输速率提出了更高的应用需求。因此，高数据率的SerDes系统一直是学术界和工业界的研究热点。本文旨在深入研究高速SerDes系统中的关键技术，并应用于JESD204C物理层接收端电路的设计实现中。本文首先对高速SerDes的系统组成及其中的均衡和时钟数据恢复两项核心技术进行了全面的研究与分析。而后结合JESD204C中物理层的相关设计要求，完成了接收端系统架构的设计。针对32Gbps NRZ的最高数据率下DFE反馈环路时序紧张的问题，本文提出了一种投机型和直接型反馈并存的3抽头半速DFE架构，放松了关键路径的时序约束，同时也节省了硬件资源。并设计了基于SS-LMS算法的DFE抽头系数自适应调整环路以及用于提供眼图收敛参考电平的阈值自适应调整环路。本文采用了基于PI的两倍过采样CDR架构, 其通过采样数据边沿的位置定位数据的理想采样点。针对DFE投机型反馈方式对均衡之后的数据边沿的影响，本文提出了对数据码型进行筛选的改进型鉴相逻辑，使得CDR环路的锁定更快更稳定。本文完成了整个接收端系统在Simulink中的建模与仿真，验证了架构方案的合理性与可行性。本文基于所提出的接收端系统架构，在28nm CMOS工艺下完成了整个系统的电路级设计实现。针对高数据率对系统模拟信号通路带宽的较高要求，本文提出了一种高密度的堆叠电感的设计方法，应用于链路中的关键节点以及模拟部分的电路设计中来拓展带宽。后仿真结果表明，模拟前端的CTLE可以实现20~24GHz频率范围内最大13.5dB以上的均衡能力，其他模拟模块的带宽均超过16GHz。接收端系统的最高工作数据率可达32Gbps或以上。本文最终完成了芯片顶层的版图设计，现已交付流片，整体芯片面积为1120um*1250um。并提出了未来芯片的回片测试方案。
High-speed SerDes is widely used in data centers, servers, and chip-to-chip data transmission due to its small number of interfaces, low channel crosstalk, and high reliability of high-speed and long-distance transmission. With the rapid development of emerging information technologies such as the Internet of Things, artificial intelligence, and cloud computing in the era of big data, the massive information interaction between systems has put forward higher application requirements for data transmission rates. Therefore, the high data rate SerDes system has always been a research hotspot in academia and industry. This paper aims to delve into the key technologies in high-speed SerDes systems and apply them to the design and implementation of receiver circuits of the JESD204C physical layer.In this thesis, the system composition of high-speed SerDes and its core technologies of equalization and clock data recovery are comprehensively studied and analyzed first. Then, combined with the relevant design requirements of the physical layer in JESD204C, the design of the receiver system architecture is completed. Aiming at the tight timing problem of DFE feedback loop under the highest data rate of 32Gbps NRZ, this thesis proposes a 3-tap half-speed DFE architecture with speculative and direct feedback, which relaxes the timing constraint of the critical path and saves hardware resources. An adaptive adjustment loop for DFE tap coefficient based on SS-LMS algorithm and a threshold adaptive adjustment loop for providing the convergence reference level of the eye diagram are designed. This thesis uses a PI-based double oversampled CDR architecture that locates the ideal sampling point of the data by the location of the edge of the sampled data. Aiming at the influence of DFE speculative feedback on the data edge after equilibrium, this thesis proposes an improved phase identification logic for filtering data patterns, which makes the locking of the CDR loop faster and more stable. In this paper, the modeling and simulation of the entire receiver system in Simulink are completed, and the rationality and feasibility of the architecture scheme are verified.Based on the proposed receiver system architecture, this thesis completes the circuit-level design and implementation of the entire system in the 28nm CMOS process. Aiming at the high requirements of high data rate on the bandwidth of the analog signal path of the system, this thesis proposes a high-density stacked inductor design method, which is applied to the design of key nodes in the link and the analog part to expand the bandwidth. The post-simulation results show that the CTLE of the analog front end can achieve a maximum equalization capacity of more than 13.5dB in the frequency range of 20~24GHz, and the bandwidth of other analog modules exceeds 16GHz. The highest operating data rate of the receiving system can reach 32Gbps or more.This thesis finally completes the layout design of the chip, and has now delivered the tape-out, with an overall area of 1120um×1250um. And the test scheme of the chip is proposed.
