云计算、大数据等技术的兴起以及线上医疗、远程办公等需求的增加，不断推动着以高速串行接口为代表的有线通信技术的发展。由于集成电路工艺发展速度的放缓，电路设计的细节考虑以及结构优化对系统的性能提升至关重要。本论文基于对高速串行接口接收机中均衡技术与时钟数据恢复技术的分析研究，开展了以下工作：首先，在40 Gb/s数据率下，基于成熟的65 nm CMOS工艺，实现了一款模拟架构PAM-4接收机。模拟前端主要包括一款具有12档调节能力的连续时间线性均衡器，在奈奎斯特频率处可以提供4.8 dB至13.1 dB的均衡能力；此外，实现了一款1/4速率12抽头判决反馈均衡器，采用了多种技术以缓解其紧张的环路时序，主要包括：采用1/4速率时钟架构缓解了第2、3、4等抽头的环路时序约束，并降低了高速时钟网络的设计难度；采用电感峰化技术提高了求和节点的带宽，通过优化抽头时序与电路结构降低了求和延时；在对传统判决器结构延时分析的基础上，提出了一种改进的1.5级判决器，通过增加一组常开的尾电流源管与一组可以提高等效跨导的交叉耦合管，使判决延时降低了约18%；优化了四路通道间的版图排列顺序，使各抽头的反馈路径长度最小，因此降低了反馈延时。基于上述优化设计，接收机最终的核心面积约0.34 mm2，在1 V的电源电压下，可以均衡约11 dB的信道衰减，误码率小于10-11，达到了4.17 pJ/b的功耗效率。其次，针对连续时间线性均衡器，提出了一种以相频响应为核心、基于群延时的优化思路，通过理论分析与仿真验证，得到了幅度衰减与额外相移的等效关系。最后，以传统模拟架构的PAM-4接收机为应用背景，对基于误差信息的波特率时钟数据恢复电路进行了分析研究。针对经典结构所存在的误差参考电压敏感性以及锁定相位不准确等问题，提出了一种基于有限状态机的相位对齐算法，并实现了一款基于此算法的波特率PAM-4时钟数据恢复电路的系统级建模，该结构无需增加额外的高速时钟与额外的判决器，与PAM-4接收机在高速资源上完全兼容。仿真结果表明，所提出的时钟数据恢复电路具有准确的锁定相位，与最佳相位之间误差不超过0.016个单位时间间隔。
The rise of technologies such as cloud computing and big data, as well as the increase in demand for online medical care and remote working, continuously promote the development of wireline communication technologies represented by high-speed serial interface. Due to the slowdown in the development of integrated circuit process, elaborate circuit design and structural optimization are critical to the performance improvement of the system. Based on the research of equalization and clock-data recovery techniques, this dissertation has the following achievements:First, a 40 Gb/s analog architecture PAM-4 receiver is realized in 65 nm CMOS process. The analog front end mainly includes a continuous-time linear equalizer with 12-step adjustment capability, which can provide 4.8 dB to 13.1 dB equalization capability at the Nyquist frequency. In addition, a quarter-rate 12-tap decision feedback equalizer is realized with a variety of techniques to relax its stringent loop timing constraint. A quarter-rate clock architecture is adopted to ease the timing constraints of the 2nd, 3rd, 4th taps, etc., and reduce the design difficulty of the high-speed clock network. The bandwidth of the summing node is improved by inductive peaking techniques, and the summing delay is reduced by optimizing the tap timing and circuit structure. A 1.5-stage slicer is proposed based on the analysis of the delay of the traditional slicer. The decision delay is reduced by about 18% by adding a pair of normally-on tail current transistors and a pair of cross-coupling transistors that can improve the equivalent transconductance. The layout order is optimized to minimize the feedback path length for each tap, thus reducing the feedback delay. Based on the above optimized design, the receiver achieves a core area of 0.34 mm2 and an energy efficiency of 4.17 pJ/bit with about 11 dB of equalization under 1 V power supply. The bit error rate is less than 10-11.Secondly, for the continuous-time linear equalizer, an optimization principle based on the phase-frequency response and group delay is proposed. Through theoretical analysis and simulation verification, the equivalent relationship between the amplitude attenuation and the additional phase shift is obtained.Finally, taking the traditional analog architecture PAM-4 receiver as the application background, the baud rate clock and data recovery circuit based on error information is analyzed and researched. Aiming at the problems of error reference voltage sensitivity and inaccurate locking phase existing in classical structures, a phase alignment algorithm based on finite state machine is proposed. A system-level modeling of a baud rate PAM-4 clock and data recovery circuit based on this algorithm is implemented. This structure does not need additional high-speed clocks and additional slicers, which is fully compatible with PAM-4 receivers in high-speed resources. Simulation results show that the proposed clock and data recovery circuit has an accurate locking phase, and the error from the optimal phase does not exceed 0.016 unit interval.
