遥感卫星通信技术具有三个非常重要的指标：高空间分辨率、高频谱利用率和高时间分辨率。其中高空间分辨率意味着可以对遥感成像区域获取更多、更精细的信息，以便后续信息处理得到更精确、更可靠的结论。高空间分辨率与采样率指标息息相关，国内高速采样系统相较国外有很大差距，在高新技术国产化的今天，对高速信号采集系统的研究非常急迫。 此外，在及时性要求不高的信号处理系统中，采集到的信号往往不会马上进行处理，而是存储在存储介质中，在需要的时候从存储介质中读取出来，并将信号还原成量化前的样子，这个过程被称为信号回放，是采集的逆过程。信号回放可以保证信息的完整性，一次采集可以进行多次回放，可以降低信号处理的难度，也经常被用在其它特殊用途，因此配套的信号回放系统的研究也是十分有必要的。 本篇论文将设计一种具有双工作模式的射频信号高速采集和回放系统，该系统具有一下主要性能指标： 1.双工作模式.采样和回放速率分别在6.4Gsps和10Gsps，分辨率分别为12bit和8bit。 2.存储深度达16TB。 该系统主要的研究工作包含： 1.系统方案的设计。包含整体方案架构的设计、设备的选型、方案的可行性分析等，求对实物的模型和进行思考，在产品供应链和成本等方面进行考量，使方案更贴合实际应用和市场化要求。 2.信号高速采集与回放时钟方案设计。在高速采集信号与回放系统系统中，信号的质量直接关乎到该系统能不能正常、稳定的工作，为了保证信号质量并成功建立传输机制，普遍会用到多个时钟芯片，使设计变得复杂。本论文时钟方案在保证系统时钟质量的同时，优化了链路时钟方案，简化了设计的复杂度。 3.JESD204B/C协议的深入研究，以及JESD204B/Cip核的设计。由于本系统需要工作在两种工作模式下，根据协议推荐线速率，需要分别工作在JESD204B或C的模式下，一般来讲，FPGA内部会带有相关ip核，但受限于FPGA厂商的通用设计和使用限制，ip核使用不太灵活，故本论文也将自研JESD204的相关ip核。 4.NVME协议的研究，以及基于Raid0的多NVME联动的ip核设计。由于本系统需要支持高速信号存储和回放的功能。一般的单个硬盘无法提供足够大的读写速度，故本论文设计基于Raid0的四个NVME并行工作的ip核，可以同时对四块U.2硬盘进行读写，满足存储和回放的速率要求。
Remote sensing satellite communication technology has three very important indicators: high spatial resolution, high spectrum utilization and high temporal resolution. The high spatial resolution means that more and finer information can be obtained from the remote sensing imaging area, so that subsequent information processing can obtain more accurate and reliable conclusions. High spatial resolution is closely related to the sampling rate index. There is a big gap between domestic high-speed sampling systems and foreign countries. Today, with the localization of high-tech, the research on high-speed signal acquisition systems is very urgent. In addition, in a signal processing system that does not require high timeliness, the collected signals are often not processed immediately, but are stored in the storage medium, read out from the storage medium when needed, and restored to What it looks like before quantization, a process called signal playback, is the inverse of acquisition. Signal playback can ensure the integrity of information. One acquisition can be played back multiple times, which can reduce the difficulty of signal processing. It is also often used in other special purposes. Therefore, it is also necessary to study the supporting signal playback system. This paper will design a high-speed RF signal acquisition and playback system with dual working modes. The system has the following main performance indicators: 1. Dual working modes. The acquisition and playback rate of working mode 1 can reach 6.4Gsps, and the acquisition and playback rate of working mode 2 can reach 10Gsps.2. The vertical resolution can reach 12bit or 8bit. 3. Storage depth up to 16TB. The main research work of this system includes: 1. The design of the system scheme. Including the design of the overall program structure, the selection of equipment, the feasibility analysis of the program, etc., as well as the physical model and thinking in order to meet the requirements of the Master of Innovation and Entrepreneurship, and consider the product supply chain and cost to make the program more suitable In line with practical application and market requirements. 2. Design of high-speed signal acquisition and playback clock scheme. In the high-speed signal acquisition and playback system, the quality of the signal is particularly important. It is directly related to whether the system can work normally and stably. In general, in order to ensure the quality of the signal and successfully establish a transmission mechanism, multiple clocks are used. chips, which complicate the design. The clock scheme in this paper optimizes the link clock scheme and simplifies the design complexity while ensuring the quality of the system clock. 3. In-depth study of JESD204B/C protocol and design of JESD204B/Cip core. Since the system needs to work in two working modes, the line rate is recommended according to the protocol, and it needs to work in JESD204B or C mode respectively. Generally speaking, the FPGA will have related ip cores inside, but it is limited by the general purpose of FPGA manufacturers. Due to design and usage limitations, the use of ip cores is not very flexible, so this paper will also develop the related ip cores of JESD204. 4. Research on NVME protocol, and design of IP core based on Raid0 multi-NVME linkage. Because this system needs to support the function of high-speed signal storage and playback. A general single hard disk cannot provide a large enough read and write speed, so this paper designs four NVME-based ip cores working in parallel based on Raid0, which can read and write four U.2 hard disks at the same time to meet the speed requirements of storage core playback.
