扇出型晶圆级封装是先进封装技术的代表之一，它适用于更薄尺寸的外形，也更适合于在封装层次进行多芯片和异质集成，目前许多公司正在开发扇出型晶圆级封装的应用，包括手机处理器、雷达模组等。本课题设计一种应用于大面阵探测器的芯片阵列扇出型晶圆级集成封装方案，以代替直接制造大面积硅芯片，并对扇出型晶圆级封装的关键技术进行研究。首先设计了一种4×4芯片阵列扇出型晶圆级封装方案，应用于探测器读出芯片的集成封装，完成可制造性工艺设计和布局布线设计，提出了试验芯片的测试方案，完成了对应试验芯片的加工与制作。对阵列芯片扇出型晶圆级封装中的翘曲问题进行了分析，研究了模塑厚度与芯片厚度对翘曲的影响规律，从封装厚度和芯片布局角度对扇出型晶圆级封装工艺和实验进行指导。接着对两层再布线（Redistribution Layer, RDL）情况下的信号质量问题进行了分析和优化。通过仿真确定了“共面传输线+补偿”布线优化方式的有效性，对本方案的两层RDL布线的电源完整性和关键信号质量进行了参数提取和仿真，模拟电源直流压降在0.1%以内，其中最复杂走线信号在80MHz频率下插入损耗-0.5dB，时域眼图仿真情况良好。最后对论文提出的封装集成方案进行了工艺的验证和分析，对工艺风险和不理想情况进行了具体分析，并提出了优化建议和措施，对加工完成的样品进行了X-Ray观测和截面观察，加工情况良好，金属布线未出现短路、断路的情况。样品翘曲测量值约为23.99μm，接近仿真值，信号链电阻通断测试情况良好。
Fan Out-Wafer Level Package is an advanced IC packaging technology. It is suitable for multi-chip and heterogeneous integration at the package level. Many companies are developing Fan Out-Wafer Level Package applications, including mobile phone, radar modules, etc. In this research, a chip array integrated scheme by Fan Out-Wafer Level Package for large area detectors is designed to replace the direct manufacturing of large-area silicon chips, and the key technologies of Fan Out-Wafer Level Package is studied.First, a Fan Out-Wafer Level Package scheme is designed for 4×4 chip array, which is applied to the detector readout chip, the manufacturability process design and layout design were completed. The plan of the test vehicle was proposed, and the processing of the test chip were completed. The warpage problem in Fan Out-Wafer Level Package is analyzed. And the influence of molding thickness and chip thickness on warpage is studied to instruct Fan Out-Wafer Level Package process experiment.Then the signal quality problems in the case of two-layer redistribution layer (RDL) are analyzed and optimized. The effectiveness of the "coplanar transmission line + compensation" wiring optimization method is determined through simulation. The power integrity and key signal quality of the two-layer RDL wiring of this scheme are extracted and simulated by EDA tools. The DC voltage IR drop of the analog power supply is within 0.1%. The insertion loss of the most complex trace signal is -0.5dB at 80MHz frequency, and the time-domain eye diagram simulation is good.Finally, the process verification and analysis of the package integration scheme proposed in this research was carried out. The risks of process and undesirable conditions were analyzed in detail, and optimization suggestions were put forward. X-Ray observation and cross-sectional observation were carried out on the processed samples. The processing condition is good, and the metal wiring of RDL has no short circuit or open circuit. The measured value of the sample warpage is about 23.99μm, which is close to the simulated value, and the signal link resistance continuity test is in good condition.
