自然界中的声音、温度、压力等物理量都是模拟信号，而绝大部分现代信号处理系统中所处理的信号都是数字信号。ADC和DAC作为连接模拟世界和数字设备的桥梁，越来越成为制约整个系统性能的瓶颈。不同的应用场景对于ADC的分辨率、采样率和功耗有着不同的要求。SAR ADC是一种适用于中等速度、中等精度的ADC结构。由于不需要模拟放大器，SAR ADC能够实现所有ADC结构中最优的能效，具有非常广阔的应用前景。COMS工艺的不断进步和电路结构的创新设计使得SAR ADC的速度不断提升，功耗不断降低。SAR ADC成为目前ADC研究的一个热点。本论文调研分析了SAR ADC的国内外研究现状和主要发展方向，研究对比了SAR ADC的同步和异步逻辑、非二进制冗余和二进制冗余方案，以及不同的电容开关时序，并基于40nm CMOS工艺研究设计了两个SAR ADC，分别为用于无线通信系统的10bit 200MS/s异步SAR ADC和用于低速数据采集系统的10bit 500KS/s同步SAR ADC。异步SAR ADC设计采用了二进制拆分重构冗余算法，以缓解高采样率下参考电压建立时间有限的问题；电容DAC采用9-2分段结构以减小采样电容值，在降低功耗的同时放宽了对参考电压缓冲器的设计要求；高3位采用分裂电容开关时序，避免了高位转换时DAC在正负参考电压之间的连续切换。DAC单位电容取值为10fF，以达到10bit匹配要求。异步SAR ADC在片上集成了基于源极跟随器的参考电压缓冲器。本论文完成了10bit 200MS/s异步SAR ADC的行为级建模和仿真、管级电路设计与前仿真、版图绘制与后仿真工作，目前已提交GDS文件，正在流片中。后仿真结果显示，在200MS/s采样率和奈奎斯特输入频率下，设计的异步SAR ADC的SNDR为55.83dB，SFDR为65.52dB，ENOB为8.98bit，功耗为6.89mW，对应的FoM为68.22fJ/conv-step。核心ADC的面积仅为0.017mm2。本论文还完成了10bit 500KS/s同步SAR ADC的行为级建模和仿真、管级电路设计和前仿真工作，该ADC的DAC单位电容设置为10fF，以满足电容匹配要求。前仿真结果显示，在500KS/s采样率和奈奎斯特输入频率下，设计的同步SAR ADC的SNDR为61.04dB，SFDR为70.41dB，ENOB为9.85bit，功耗为9.36μW，对应的FoM为20.28fJ/conv-step。

The physical quantities in nature, such as sound, temperature and pressure are analog signals; while most modern signal processing systems deal with only digital signals. As the bridge connecting the analog world and digital devices, ADC and DAC are increasingly becoming the bottleneck limiting the entire system performance. There are different requirements for the ADC resolution, sampling rate, and power consumption for different applications. SAR ADC is a structure suitable for medium speed and medium precision. As no analog amplifier needed, it can achieve the best power efficiency among all ADC structures and widely used in electronic systems. With CMOS technology scaling and circuit design innovations, the speed of SAR ADC is improved and the power consumption is reduced, leading to a popular ADC research topic at present.This thesis investigates and analyzes the state-of-the-art research of SAR ADC, and compares synchronous and asynchronous logic, non-binary redundancy and binary redundancy schemes, and different capacitor switching sequence of SAR ADC. Based on 40nm CMOS technology, two SAR ADCs are designed in this thesis, a 10bit 200MS/s asynchronous SAR ADC for wireless communication systems and a 10bit 500KS/s synchronous SAR ADC for low-speed data acquisition system.In the asynchronous SAR ADC design, binary-scaled recombination redundant algorithm is introduced to mitigated the influence of limited reference voltage settling time under high sampling rate. The capacitive DAC adopts a 9-2 segmented structure to reduce the sampling capacitance, and therefore reduced power consumption and relaxed the design requirements of reference voltage buffer. The MSB to MSB-2 adopts split-capacitor switching sequence to prevent DAC from continuously switching between the two reference voltages during MSBs’ conversion. The unit capacitance of DAC is 10fF to meet the matching requirement of 10bit resolution. The asynchronous SAR ADC also integrates a reference voltage buffer based on source follower on the chip. This thesis has completed the behavior-level modeling and simulation, transistor-level circuit design and pre-simulation, layout design and post-simulation work of the 10bit 200MS/s asynchronous SAR ADC, now the GDS file has been submitted to foundry for tape-out. The post-simulation results show that with 200MS/s sampling rate and a Nyquist input frequency, the designed asynchronous SAR ADC achieves an SNDR of 55.83dB and an SFDR of 65.52dB with an ENOB of 8.98bit. The power consumption is 6.89mW, corresponding to a FoM of 68.22fJ/conv-step. The area of core ADC is only 0.017mm2.This thesis has also completed the behavior-level modeling and simulation, transistor-level circuit design and pre-simulation of the 10bit 500KS/s synchronous SAR ADC. 10fF DAC unit capacitance is chosen in this ADC for the capacitance matching requirement. The pre-simulation results show that with 500KS/s sampling frequency and a Nyquist input frequency, the designed synchronous SAR ADC achieves an SNDR of 61.04dB and an SFDR of 70.41dB with an ENOB of 9.85bit. The power consumption is 9.36μW, corresponding to a FoM of 20.28fJ/conv-step.