随着CMOS技术的不断发展，数字锁相环(DPLL)在时钟生成以及频率调制方面具有广阔的应用前景。但是通常的数字锁相环对高性能时间数字转换器(TDC)的需求极大地降低了电路全数字化实现带来的优势，一般需要复杂的电路结构以及额外的校准电路来进行性能补偿。而Bang-Bang数字锁相环(BBPLL)采用了一位TDC，即Bang-Bang鉴相器(BBPD)，不受多位TDC面积和功耗的影响，可以实现超低电压和更紧凑的设计。虽然基于BBPD设计的Bang-Bang数字锁相环克服了时间数字转换器面临的分辨率、动态范围、线性度以及功耗之间相互制约的设计瓶颈，使得低电压的锁相环设计成为可能。但是BBPD面临其固有的非线性问题，尤其在分数工作模式下使得锁相环的强非线性因素影响急剧上升，带内噪声以及杂散性能恶化。本文针对分数模式下Bang-Bang数字锁相环面对的这些问题，围绕锁相环噪声提高完成了研究和分析。本文首先介绍了分数型数字锁相环的基本结构、原理，通过建立线性化模型进行了基本的分析，重点研究了影响分数数字锁相环性能的关键因素及其噪声来源。由于Bang-Bang数字锁相环非线性问题的存在，导致很难直接对其建立线性化模型并采用反馈理论进行分析。因此通过等效BBPD的方法建立了对应的近似线性化模型，对其在分数模式下工作时噪声恶化的原因进行了分析。基于此提出了改善锁相环性能的关键技术，同时也介绍了数字锁相环在应用于调制电路时的一些常用的技术方法。最后根据对分数ΔΣ BBPLL噪声的理论分析以及所提出的噪声优化方法，采用65nm CMOS工艺设计了两种锁相环电路：一款为低噪声的分数型Bang-Bang数字锁相环电路，其在输出2.48GHz时钟频率下可以获得近-100dBc/Hz的带内噪声以及-60dBc的分数杂散。另一款为基于Bang-Bang数字锁相环的两点式GFSK调制器电路，可以实现2.4GHz下1Mb/s的GFSK调制。测试结果表明，该调制器中的锁相环带内相位噪声得到了约13dB的改善，达到-91.17dBc/Hz，分数杂散降低了约17dB，达到了-62.3dBc。

With the development of CMOS technology, the digital phase-locked loop (DPLL) is promising for robust clock generation and modulation. The need of a high performance time-to-digital converter (TDC), however, mitigates the strong features of all-digital implementation. To compensate for the limited performance of the conventional multi-bit TDC, complex architectures or calibrations are needed. Not suffering from the power-hungry and area-consuming multi-bit TDC, the DPLL employing a single bit TDC, namely the bang-bang phase detector (BBPD), enables an ultra-low voltage and compact design.Although the bang-bang digital phase-locked loop (BBPLL) based on a BBPD relaxes the design complexity of the TDC in terms of resolution, dynamic range, linearity and power consumption and is a viable PLL architecture for low-voltage clock generation, the inherent nonlinear characteristic of the BBPD makes it difficult to design a low-noise fractional-N PLL due to the phase- folding effect. In this paper, we will focus on how to improve the noise performance of BBPLL.Firstly, the basic analysis of the fractional-N DPLL based on a linear model is performed. We show several key design aspects by considering several noise sources. Because of the nonlinear characteristic of the BBPD, the linear analysis is done with an equivalent linear model of the BBPD, explaining why the in-band phase noise is degraded in the fractional-N mode. Based on the analysis, several key techniques to improve the performance of the fractional-N BBPLL for clock generation and modulation are presented.Based on the analysis of the fractional-N BBPLL and the proposed techniques, two fractional-N BBPLLs are implemented with 65nm CMOS technology. One is a low-noise fractional-N PLL with the output frequency of 2.48GHz, achieving -100dBc/Hz in-band noise and -60dBc fractional spur. The other is a two-point GFSK modulator based on the fractional-N BBPLL, which can achieve 1Mb/s GFSK modulation at 2.4GHz. The testing results show that the BBPLL achieves -91.17dBc/Hz in-band noise with an improvement of about 13dB, and the fractional spur is reduced to -62.3dBc with 17dB improvement.