人工智能应用的发展，对计算和存储提出了更高的需求。而基于传统“冯诺依曼”架构的计算硬件面临“存储墙”的挑战，无法满足高性能、低功耗、低延时的处理需求。为了突破“冯诺依曼”瓶颈，基于忆阻器的存算一体架构可以实现数据的原位存储与计算，从而大大降低计算过程中频繁数据搬移带来的功耗和延时，因此成为了业界与学术界研究的重点。目前，对该领域的研究还面临诸多挑战，其中一个挑战是在对硬件设计实现的验证工作中，由于忆阻器阵列的计算过程是模拟的，输出存在误差累积问题，因此其验证工作往往通过数字仿真或数模混仿来完成，前者难以实现有效的功能验证，后者耗费时间过长。而电路级验证则缺少对忆阻器阵列模块的完整验证。此外，还缺乏专用的验证可重用IP。为解决以上验证工作中存在的困难，本论文主要进行了如下工作：(1)研究了适用于电路级验证的通用验证方法学(Universal Verification Methodology，UVM)及其验证技术，对多种可提高验证效率的机制进行了分析。(2)研究了存算一体神经元处理单元(Neuronal Processing Unit，NPU)芯片特点，得出了其各层次的验证需求和待测点，并提出了针对忆阻器阵列模块的验证方案。(3)搭建了UVM验证平台及其顶层测试环境，通过验证平台各组件和组件间的通信实现，构建了可对该NPU重用的电路级验证环境。(4)最后按各层的验证需求编写了3大类测试用例进行验证分析，实现了待测功能的100%的覆盖，并通过异常用例时的报错证明了针对忆阻器阵列模块的验证方案的有效性。本论文工作中的主要创新点有：(1)为解决存算一体NPU芯片电路级验证中忆阻器阵列模块难以实现完整验证的问题，分别提出了在NPU验证平台中对其进行输入接口控制时序检查、输出随机数注入的验证方案，完善了电路级验证工作，并提前预估了一定范围内的随机偏差，且仿真用时相比数模混仿减少了两个数量级。(2)为提高验证效率，结合UVM的优势及NPU芯片特点，利用Python语言构建了自动代码生成脚本，自动生成验证平台组件框架，使NPU验证平台的搭建时间减少了约30%，为NPU验证平台的全面自动化生成起到了一定的探索作用。本论文工作实现了面向忆阻器NPU的验证平台，该平台完善了对忆阻器阵列模块的验证工作，还可以预估输出的一定随机偏差，并具有一定的重用性，对基于忆阻器阵列的存算一体芯片的电路级验证工作具有一定的借鉴作用。

The development of artificial intelligence application has put forward higher demand for computing and storage. However, the traditional Von Neumann architecture based computing hardware is facing the challenge of Memory Wall, which can not meet the needs of high performance, low power consumption and low delay. In order to break through the bottleneck of Von Neumann, the computing-in-memory architecture based on ReRAM can realize in-situ storage and calculation of data, which greatly reduces the power consumption and delay caused by frequent data migration in the calculation process, so it has become the focus of the research in the industry and academia. At present, the research in this field is still facing many challenges, one of which is in the verification of hardware design and implementation. Because the calculation process of the ReRAM array is analog and the output has error accumulation problem, the verification work is usually completed by digital simulation or digital analog simulation. The former is difficult to realize effective functional verification, and the latter takes too long time. However, the circuit-level verification lacks the complete verification of the ReRAM array module. In addition, there is a lack of dedicated authentication reusable IP.In order to solve the difficulties in the above verification, the main work of this paper is as follows: （1） the Universal Verification Methodology and its verification technology are studied, and various mechanisms which can improve the verification efficiency are analyzed. （2） The characteristics of the computing-in-memory Neuronal Processing Unit chip are studied. The verification requirements and the points to be measured are obtained at all levels. The verification scheme for the ReRAM array module is proposed. （3） The UVM verification platform and its top-level test environment are built. Through the communication between the components and components of the verification platform, a circuit-level verification environment can be reused for the NPU. （4） Finally, three kinds of testcases are written according to the verification requirements of each layer to verify and analyze, which can cover 100% of the functions to be tested. The validity of the verification scheme for ReRAM array module is proved by error reporting in different common examples.The main innovations in this paper are: （1） to solve the problem that the ReRAM array module is difficult to realize complete verification in the circuit-level verification of NPU chip, the verification scheme of input interface control timing check and output random injection in NPU verification platform is proposed respectively, and the circuit-level verification work is improved, The random deviation in a certain range is estimated in advance, and the simulation time is reduced by two orders of magnitude compared with the mixed simulation. （2） In order to improve the verification efficiency, combined with the advantages of UVM and the characteristics of NPU chip, the automatic code generation script is constructed by Python language, and the component framework of the verification platform is automatically generated, which reduces the construction time of NPU verification platform by about 30%, which plays a certain exploratory role in the overall automatic generation of NPU verification platform.This paper implements the verification platform for NPU based on ReRAM. It improves the verification of ReRAM array module, and can estimate the random deviation of output, and has certain reusability. It can be used for reference for circuit-level verification of computing-in-memory chip based on ReRAM array.