近年来随着物联网技术的发展以及应用场景的拓展，越来越多的物联网设备需要同时兼容多种物联网协议以满足应用需求。传统单模单频的射频解决方案不利于减小物联网设备的体积和设计生产成本，因此支持多模多频的物联网收发机芯片逐渐成为未来的发展趋势。本文的目标是提出一种能够兼容NB-IoT、ZigBee、BLE三种主流低速率物联网协议的低功耗低成本的射频发射机架构并完成其中部分关键模块的设计。文中提出了一种基于两点调制与相位选通器的发射机架构。该发射机具有较高的可重构性，能够在较小的芯片面积和较低的功耗下实现对三种协议的支持。本文根据协议要求以及文献调研确定了该发射机中的相位选通器、功率放大器（PA：Power Amplifier）、低噪声线性稳压器（LDO）三个关键模块的设计目标，并完成了相应的电路实现。文中相位选通器采用了分段式结构，能够有效地减少幅度控制单元在高位翻转时引入的毛刺。此外为了避免幅度控制单元在同时开启或关断时对共同的参考电压产生影响，在相位选通器的开关处引入了低交叉点驱动电路。最终相位选通器可以实现不低于5.5bit的有效幅度控制位数。文中PA采用了共源共栅结构的AB类功率放大器，通过调节共栅管偏置电压以及片外的供电电压，能够在10dBm以及0dBm两个输出功率等级之间切换。最终PA在10dBm输出等级时能够在低、中、高三个频段分别实现12.7dBm、14dBm、13.8dBm的1dB压缩点以及21.7%、36.5%、39.25%的漏端效率。本文中PA以及相位选通器模块采用65nm CMOS工艺进行设计，核心部分总面积仅为0.36mm2。后仿真结果显示，当输出功率为10dBm时，3阶与5阶反向互调均能够满足低于-36dBc的要求，同时当输出功率为0dBm时，低中高三个频段的整体功耗分别为20.6mW、20.5mW、25.3mW。此外，本文中还为发射机的压控振荡器设计了一个采用自适应偏置技术的超低输出噪声全片上集成的LDO，并在180nm CMOS工艺下进行了结构与功能的验证。最终测试结果显示，该低噪声LDO能够实现低至6.2μV的积分噪声（10Hz~100KHz），以及180mV的瞬态响应（99mA@100ns）。
With the development of IoT 's (Internet of Things) technology and application scenarios, more and more IoT devices need to support multiple IoT protocols to meet application requirements. Traditional single-mode single-band RF (Radio Frequency) solutions are not conducive to reducing the volume and cost of IoT devices. Therefore, IoT transceiver chips that can support multi-mode and multi-band have become the future development trend. This thesis aims to propose a low-power and low-cost RF transmitter architecture, which is compatible with NB-IoT, ZigBee, and BLE, and finally completes the design of some key modules in the transmitter.This thesis proposes a transmitter architecture based on two-point modulation and Phase MUX. Due to its high reconfigurability, the transmitter can support the three standards in a small chip area and low power consumption. This thesis is responsible for designing the Phase MUX, Power Amplifier (PA), and LN-LDO (Low Noise Low Dropout Regulator) in the transmitter. The design indicators of the three modules are derived from the RF transmission requirements and literature research.The Phase MUX in this thesis adopts a segmented structure, which can effectively reduce the glitch generated when the MSB (Most Significant Bit) unit is flipped. In addition, a low cross-point latch driver circuit is used here to ensure that the common reference voltage will not be affected when multiple Phase MUX units are turned on and off at the same time. The Phase MUX can achieve an effective number of amplitude control bits (ENOB) more than 5.5bit, while achieving a dynamic range above 42dBc.The PA in this thesis uses a fully differential class AB power amplifier with a cascode structure. By adjusting the bias voltage of the common gate transistor and the power supply voltage of the PA, two output power level of 0dBm and 10dBm can be realized. Finally, when the PA output power is 10dBm, the 1dB compression point (OP1dB) of 12.7dBm, 14dBm, and 13.8dBm and the drain efficiency of 21.7%, 36.5%, and 39.25% can be achieved in the low, middle and high bands respectively.PA and Phase MUX module are designed in the 65nm CMOS and occupy a chip area of 0.36mm2. The post-simulation results show that its CIM3&CIM5 can meet the requirement of less than -36dBc under 10dBm output. At the same time, when the output power is 0dBm, the overall power consumption of the low, medium and high bands are 20.6mW, 20.5mW, and 25.3mW respectively.In addition to the two modules, this article also designed an ultra-low output noise fully integrated LDO for the VCO in the transmitter using adaptive bias technology, its structure and function are verified in 180nm CMOS tech. Finally, measurement results show that this low-noise LDO can achieve an integrated output noise of 6.2uV and a transient response of 180mV (99mA@100ns).
