模数转换器作为连接模拟世界与数字世界的接口，是电子系统中不可或缺的一部分，更是第五代移动通信中的关键技术模块。如何实现高性能，尤其是高速高精度的模数转换器，一直是工业界和学术界研究的热点。得益于先进工艺的发展，利用数字电路进行辅助校准设计的方式，也成为了新的研究方向。 本文首先对高性能模数转换器的架构进行调研，总结出单通道采用流水线结构，多通道采用时间交织结构，是实现高速高精度的首选架构。接着探究了流水线和时间交织结构转换器中的误差来源，并进行了详细的分析。随着工艺的进步，低功耗的需求，电容失配，运放有限增益的问题尤为突出。此外，增益的温漂问题，时间交织结构中采样时刻偏差的问题，都成为了限制模数转换器性能的瓶颈。因此，本论文对现有的校准技术进行研究，结合不同校准方式的优点，设计了用于单通道和多通道时间交织结构的校准算法。 本文设计的用于流水线模数转换器的校准算法具有以下特点：（1）从系统架构层面，对流水线的前三级采用前台校准，并将第一级和后级的所有数据用于后台校准。（2）为了提升电路的动态特性，在前三级电路的输入注入抖动，打散频谱中固定位置的杂散。（3）利用MDAC中的抖动电容作为前台校准的辅助电容，前台校准方法简单，校准速度快。（4）在前台校准中，采用交换电容的方式，并且利用零输入位置，测量各个电容的实际权重。（5）在后台校准中，当电路中存在未校准的误差时，利用同一输入下不同抖动的输出差异，进行最小均方误差的收敛。（6）前台校准可以纠正由电容失配和运放有限增益带来的误差，后台校准可以实时跟踪运放增益的变化而进行校准。针对时间交织结构中的采样时刻偏差问题，设计的校准算法具有以下特点：（1）采用基于统计的相关性原理，无参考通道的后台实时校准。（2）采用数字域检测，模拟域纠正的数模混合校准。 单通道校准算法用于一款16-bit 250MS/s Pipelined ADC，芯片测试结果表明，开启前台校准，在70MHZ，-1dBFS输入下，SNR=74.14dBFS，SFDR=83.63dBFS，ENOB=11.98bit。在小信号幅度下，打开抖动开关，SFDR提升10dB。对于时间交织结构的校准算法用于一款14-bit 500MS/s 双通道交织结构。开启校准，由采样时刻偏差导致的杂散被压制到-95dB以下。芯片测试结果证明算法的实用性。
As an interface connecting the analog world and the digital world, the analog-to-digital converter is an indispensable part of the electronic system, and it is also a key technology module in the fifth generation mobile communication. How to achieve high performance, especially high-speed and high-precision analog-to-digital converters, has been a research hotspot in industry and academia. Thanks to the development of advanced technology, the use of digital circuits for auxiliary calibration design has also become a new research direction. This article first investigates the architecture of a high-performance analog-to-digital converter and concludes that a single channel uses a pipeline structure, and multiple channels use a time-interleaved structure, which is the preferred architecture for achieving high speed and precision. Then explored the sources of error in the pipeline and time-interleaved structure converter, and carried out a detailed analysis. With the progress of process and the requirement of low power consumption, the problem of capacitor mismatch and the finite gain of the op amp is particularly prominent. In addition, the temperature drift of the gain, and the problem of timing skew in the time-interleaved structure, have all become bottleneck that limits the performance of the analog-to-digital converter. Therefore, the existing calibration technology is studied and summarized, combined with the advantages of different calibration methods, a set of calibration algorithms that can be used in single-channel and time-interleaved structures is designed. In this paper, the calibration algorithm used for pipelined analog-to-digital converter has the following characteristics: (1) From the system architecture level, the front-end calibration is used for the first three stages of the pipeline, and the data of the first and backend stages are used for background calibration . (2) In order to improve the dynamic characteristics of the circuit, dither are injected into the input of the first three stages to disturb the fixed-position spurs in the spectrum. (3) Using the dither capacitor in MDAC as the auxiliary capacitor for front-end calibration, the front-end calibration method is simple and the calibration speed is fast. (4) In the foreground calibration, the method of exchanging capacitor is used, and the actual weight of the each capacitor is measured using the zero input position. (5) In the background calibration, when there is an error in the circuit, use the output difference of different dither under the same input to perform the method of minimum mean square error convergence. (6) The front-end calibration can correct errors caused by capacitor mismatch and the finite gain of the op-amp. The back-end calibration can track the change of the op-amp gain in real time and perform calibration. Aiming at the timing skew in the time-interleaved structure, the designed calibration algorithm has the following characteristics: (1) Based on statistical correlation principle, background real-time calibration without a reference channel. (2) Adopting digital domain detection and digital-analog hybrid calibration of analog domain correction. The single-channel calibration algorithm is used for a 16-bit 250MS/s Pipelined ADC. The chip test results show that with the foreground calibration turned on, under 70MHZ, -1dBFS input, SNR = 74.14dBFS, SFDR = 83.63dBFS, ENOB = 11.98bit. At a small signal amplitude, the SFDR is increased by 10dB when the dither switch is turned on. The calibration algorithm for the time interleaved structure is used in a 14-bit 500MS/s dual-channel time-interleaved structure. When the calibration is turned on, the spurs caused by the timing skew are suppressed to below -95dB. The chip test results prove the practicability of the algorithm
