CMOS图像传感器是实现数字图像信息采集的核心元件，广泛应用于各类信息系统之中。由于应用场景不断拓宽，加之人们对成像质量的要求不断提高，高分辨率成为了CMOS图像传感器研究制造的重要趋势之一。随着分辨率的提升，像素尺寸不断缩小，系统内电路规模增大同时工作速度越来越快，CMOS图像传感器在噪声、动态范围、功耗等多个方面会面临新的问题与挑战。本文针对高分辨率CMOS图像传感器的问题，从噪声、动态范围与功耗三个角度，研究适宜于高分辨率CMOS图像传感器的读出电路关键技术，重点关注基于列并行单斜坡式ADC (single-slope ADC, SS-ADC) 读出电路架构下的系统及电路结构和设计方法。本文主要工作如下：概述了CMOS图像传感器的基本原理，系统介绍各项指标，对相关研究工作进行了总结。在对CMOS图像传感器读出电路噪声分析的基础上，提出了两种低噪声设计方法，包括SS-ADC的起始点预放大方法和像素阵列电容方法。分析了在考虑光子散粒噪声影响下调整SS-ADC量化步长的原则与方法，提出了一种基于开关电容的增益自适应结构，给出了两种具体的电路实现结构，对增益自适应方法的非线性问题给出了分析和校准方法。对列并行读出电路的关键模块进行了低功耗设计，提出了一种开关电容控制的低功耗动态偏置比较器和一种低翻转次数的双向双边沿计数器。基于TSMC 180nm工艺实现了一款低功耗的列并行增益自适应SS-ADC，列平均功耗仅为63.2\(\mu W\)，经过校准后取得了13bit的动态范围。基于提出的列并行读出电路结构，采用SEC 90nm 1P3M CIS BSI工艺实现了一款500万像素的CMOS图像传感器系统芯片，像素尺寸仅为1.12\(\mu m\)，列ADC面积为2.24\(\times\)365\(\mu m^2\)，系统总功耗为135.8mW，随机噪声为1.2\(e^-\)，动态范围为71.5dB，\(FoM_1\)值为1.08\(e^-\cdot nJ/pixel\)，\(FoM_2\)值为0.29\(e^-\cdot pJ/step\)。测试结果显示，该CMOS图像传感器在分辨率及能效方面具有较好的性能，证明了本论文所研究内容的正确性和有效性。
CMOS image sensors are the core components in a digital imaging system, and widely used in various information systems. With application in an increasing number of fields and people demanding higher imaging quality, high resolution has become an important trend in the research and manufacturing of CMOS image sensors. As the resolution increases, the pixel size continues to shrink, and the circuit scale becomes larger and the circuits operate faster. CMOS image sensors will face new problems and challenges in many aspects such as noise, dynamic range, and power consumption. This thesis focuses on the problems of high-resolution CMOS image sensors and studies the key technologies of the readout circuit of high-resolution CMOS image sensors from the aspects of noise, dynamic range and power consumption, especially in the system and circuit design method based on the column-parallel single-slope ADC (SS-ADC) readout circuit architecture. The main work of this thesis is as follows:The basic principle of CMOS image sensor and related research are summarized.Based on the noise analysis of the CMOS image sensor readout circuit, two low-noise design methods are proposed, including the initial point pre-amplification method and the pixel array capacitance method.The principle and method of adjusting the quantization step size of SS-ADC under the influence of photon shot noise are analyzed. A gain adaptive structure based on switched capacitor is proposed, and two specific circuit implementation structures are given to realize the structure. The nonlinearity of the gain-adaptive method is analyzed, and the calibration method is given.A switched-capacitor controlled dynamic bias comparator and a flip-reduced up/down double-data-rate counter are proposed to reduce the power consumption of the readout circuits. A column-parallel low-power gain-adaptive SS-ADC chip is fabricated in the TSMC 180 nm CMOS process. A single-column ADC consumes a total power of 63.2 \(\mu W\) and acquires 13-bit linear output.Based on the proposed column-parallel readout circuit structure, a 5-megapixel CMOS image sensor system chip is implemented using the SEC 90nm 1P3M CIS BSI process. The pixel size is only 1.12\(\mu m\), and the column ADC area is 2.24\(\times\)365\(\mu m^2\). The power consumption of the system is 135.8mW and the temporal noise is 1.2\(e^-\) and the dynamic range is 71.5dB. The CIS system achieves the \(FoM_1\) of 1.08\(e^-\cdot nJ/pixel\) and \(FoM_2\) of 0.29\(e^-\cdot pJ/step\). This work achieves a better performance which proves the effectiveness of the work of this thesis.
