在如今的信息化军事战场中，为全面提高战机战舰的作战能力，有源相控阵雷达逐渐受到国防军事领域的青睐。在提升相控阵雷达性能的进程中，其射频前端各模块的指标牵动着整个系统的性能。本文基于一个Ka波段四通道相控阵雷达芯片工程项目，着重研究了射频前端关键模块的设计技术和方法。本文设计实现了中心频率为35GHz，带宽1GHz的Ka波段四通道相控阵雷达芯片的收发开关、低噪声放大器、功率放大器、缓冲放大器模块。本文首先分析了各模块对带宽、增益、噪声、线性度等指标的贡献度，并据此对各个模块的性能指标进行规划，确定了四个模块的具体性能指标。移相器前及功率合成网络后的收发开关采用串并联开关管结构，损耗仅为1.5dB，IP1dB≥9.5dBm。天线后端收发开关为匹配大功率PA而采用了体端悬浮和晶体管堆叠技术，IP1dB可达19dBm，收发支路损耗为2dB。二者的S11及S22带宽均≥30GHz。在低噪声放大器的设计中，噪声系数受版图及晶体管寄生电容影响，很难被降低。因此，我们在设计中使用级联的共源共栅结构提高隔离度并抑制栅漏电容的前馈效应。在中间节点插入interstage电感使噪声系数降低0.5dB达到3.4dB且增益提高7.2dB达到26.2dB。-1dB带宽≥4.5GHz。噪声系数工作频带内波动≤0.1dB。功率放大器的设计中，单路功放受晶体管击穿电压的限制和巴伦设计的限制，输出1dB压缩点最高仅为13~14dBm。在本设计中采用了两路功率合成结构，输出巴伦采用顶层及次顶层金属偏移尽量提高Q值及耦合系数，其损耗仅为1.3dB，最终功放实现了16dBm的输出1dB压缩点。其峰值增益能够达到23.9dB，且1dB带宽为4.8GHz。34.5~35.5GHz范围内，S11≤-15dB，S22≤-8dB。针对模块级联后通路带宽受限的问题，本设计中插入了1dB带宽达到9GHz以上的宽带缓冲放大器来弥补链路的增益和带宽。该Buffer具有一定的通用性，峰值增益16.3dB，OP1dB≥7dBm，能够满足三个位置上的带宽、增益以及线性度需求。收发开关与低噪放级联后，天线端看到的噪声系数为5.2dB；与功放级联后，天线端OP1dB为13.5dBm。该芯片使用TSMC CMOS 65nm工艺实现，四通道版图对称，芯片面积7.2 mm × 3.6 mm。后仿真结果能够达到系统性能指标的目标。
Nowadays, in information-based military battlefields, in order to improve the overall combat capabilities of fighters and warships, active phased array radar is gradually favored by the defense military. In the process of improving the performance of phased array radar, the performance of the whole system is affected by the indicators of its RF front-end blockes. Based on a Ka-band four-channel phased array radar chip project, this thesis studies the design technology and methods of the key blocks of the RF front-end. In this thesis, the T/R switch, low noise amplifier, power amplifier and buffer of Ka-band four-channel phased array radar chip with center frequency of 35GHz and bandwidth of 1GHz are designed and implemented. According to the requirements of system performance indicators, this thesis analyzes the contribution of each block to bandwidth, gain, noise, and linearity. Accordingly, the performance indicators of each block have been planned. The specific performance indicators of the four blocks are also determined. The T/R switch before the phase shifter and after the power synthesis network adopts the series-parallel switch structure, achieving the insertion loss of only 1.5dB and IP1dB≥9.5dbm. In order to match the high-power PA, the T/R switch behind the antenna adopts body-floating and stacked-transistor technology. The IP1dB reaches 19dBm, and the insertion loss of the transceiver branch is 2dB. The bandwidth of S11 and S22 of both T/R switch≥30GHz. In the design of the low noise amplifier, the noise figure is affected by the layout and the parasitic capacitance of the transistor, which is difficult to be reduced. Therefore, cascaded cascode structure is used in our design to improve the isolation and inhibit the feed-forward effect of C_gd. Inserting an interstage inductor at the middle node reduces the noise factor by 0.5dB, which reaches 3.4dB and increases the gain by 7.2dB, which reaches 26.2dB. BW-1dB≥4.5GHz. The fluctuation of noise factor in the working frequency band≤0.1dB. In the design of the power amplifier, the single-way structure’s output power is limited by the breakdown voltage of the transistor and the design difficulty of balun. The maximum output 1dB compression point is only 13 ~ 14dBm. In this design, a two-way power combining structure is used. The output balun adopts the top and second top metal offsets structure to maximize the Q factor and the coupling coefficient. Its loss is only 1.3dB, and PA finally realizes an output 1dB compression point of 16dBm. The post simulation shows 23.9dB peak gain and 4.8GHz BW-1dB. In the range of 34.5 ~ 35.5GHz, S11≤-15dB, S22≤-8dB.In order to solve the problem that the channel bandwidth is limited after the blocks are cascaded, a broadband buffer amplifier with 1dB bandwidth of more than 9GHz is inserted to compensate for the gain and bandwidth of the RF chains. The buffer is versatile, which shows 16.3dB peak gain and 7dBm OP1dB, and can meet the bandwidth, gain and linearity requirements of three locations. When the T/R switch is cascaded with the low noise amplifier, the noise factor at the antenna is 5.2dB; when it is cascaded with the power amplifier, the OP1dB at the antenna is 13.5dBm.The chip is implemented using TSMC CMOS 65nm process, the four-channel layout structure is symmetrical, and the chip area is 7.2 mm × 3.6 mm. The post-simulation results met the requirements of system performance.
