智慧天网创新工程（TSN）是以中轨卫星为骨干，构建的不依赖地面光纤、全球覆盖的空间信息网络，旨在构建安全可靠的互联网络基础设施。本文研究了TSN系统馈电链路通信体制设计和实现，其具有着超宽带、高数据吞吐率、无用户多址、自适应编码调制的特征。而宽带信号和高阶调制对物理器件的非线性更敏感，信道为频率选择性信道，且对系统同步和估计的性能要求更高。同时，受限于解调器物理设备运行速率，需要多路并行化处理。首先，本文研究了数据辅助的物理层帧结构设计。本文提出了一种新的适用于馈电链路通信的帧结构。该结构使用多段重复的LP序列作为训练序列，能够实现在本系统支持的最低码率下，存在多径信道和载波频偏的条件下，稳定精确地实现帧同步、信道估计、载波同步、信噪比估计等功能。帧体使用短训练序列UW和数据符号均匀间隔排列的结构，可以实现相位估计、信道均衡保护和频域的迫零均衡。其次，针对信道编码，由于缺乏码率和码长均与本系统设定相一致的LDPC码，本文比较和选择了不同类型的LDPC码，对5G LDPC码进行了改造，设计了1/2，2/3，5/6，8/9四种LDPC码，适配于本系统的自适应编码调制的信道编码的需求。本文实现了分层译码的译码架构，能够进行多路并行化处理，可以达到高速译码的要求。针对LDPC码在硬件结构中量化引起的性能损失，本文提出了非均匀量化的软信息量化方案，相比于均匀量化，在6比特量化的情况下，对于高阶APSK有大约0.4 ~0.5dB的性能提升。最后，本文使用FPGA实现了馈电链路上下行通信的工程系统，包括信号调制解调、LDPC编码译码、时间同步等功能。为适应高速解调的需求，实现了对接收信号的16路并行处理，以及对估计、同步、均衡等模块的并行化。硬件测试结果表明，在给定的硬件资源下，系统完成了帧同步，时钟同步，载波同步，高信噪比系统误码率为零。性能测试给出，硬件系统性能与理论仿真性能有约2dB损失。
The TSN system is based on middle earth orbit satellites, which builds a spatial information network that does not rely on terrestrial optical fibers and has global coverage. It aims to build a safe and reliable interconnected network infrastructure. This thesis studies the design and implementation of the feeder link communication system of the TSN system, which has the characteristics of ultra wide band, high data throughput, without user multiple access, and adaptive coding and modulation scheme. Broadband signals with high-order modulation are more sensitive to the nonlinearity of electronic devices. They face a frequency-selective channel and require better performance on synchronization and estimation. At the same time, due to the limited operating speed of the electronic device of the demodulator, multiple parallel processing is required.First of all, this paper studies the data-aided physical layer frame structure design. This paper proposes a new frame structure suitable for feeder link communication. This structure uses multiple repeated LP sequences as training sequences, which can achieve stable and accurate frame synchronization, channel estimation, carrier synchronization, and signal-to-noise estimation with the presence of the lowest code rate supported by the system, multipath channel and carrier frequency offset. The frame body uses a structure with a short training sequence UW and data symbols arranged at even intervals to achieve phase estimation, channel equalization protection, and zero-forcing equalization in the frequency domain.Secondly, for the channel coding, due to the lack of LDPC codes whose code rate and code length are consistent with the settings of this system, this paper compares and selects different types of LDPC codes, and transforms the 5G LDPC code to adapt to this system According to the needs of adaptive coding and modulation, four LDPC codes of 1/2, 2/3, 5/6 and 8/9 are designed. The decoding architecture of layered decoding is realized, and multi-channel parallel processing can be performed, which can meet the requirements of high-speed decoding. In view of the performance loss caused by the quantization of LDPC codes in the hardware implimentation, this paper proposes a non-uniform quantization scheme of soft information. Compared with uniform quantization, in the case of 6-bit quantization, it has a performance improvement of 0.4~ 0.5 dB for high-order APSK. Finally, this paper uses FPGA to realize the engineering system of the uplink and downlink communication of the feeder link, including signal modulation and demodulation, LDPC codec, time synchronization and other functions. To meet the needs of high-speed demodulation, 16 parallel processing of received signals and parallelization of modules such as estimation, synchronization, and equalization are realized. The hardware test results show that under the given hardware resources, the system has completed frame synchronization, clock synchronization, carrier synchronization, and zero bit error rate in a high signal-to-noise ratio setting. The performance test shows that there is a loss of about 2dB between the hardware system performance and the theoretical simulation performance.
