连续时间Sigma Delta调制器被广泛应用于无线通信系统中，相比于其他几种类型的模数转换器，其高精度、输入网络负载低以及自带抗混叠滤波器等特性在系统集成方面有着独特的优势。随着无线通信速度的不断提升，如何设计高宽带的连续时间Sigma Delta调制器成为了研究热点。本文设计一款可应用于5G通信系统的宽带连续时间Sigma Delta调制器。调制器采用前馈-反馈混合型单环结构，过采样率12.5，量化器为四比特，环路滤波器为三阶，加入一阶连续时间噪声耦合提高环路的噪声整形效果。环路延时设置为半个时钟周期，采用PI-element方法补偿环路延时以节约功耗。内部的积分器为有源RC型，量化器中的比较器单元由静态预防大器和Strong_ARM型锁存器组成，反馈DAC为不归零型互补电流舵式。为校准反馈DAC单元之间的随机失配误差，采用基于逐次逼近原理的DAC失配前台校准电路。积分器中的运算放大器为三级级联结构，通过前馈补偿的方式，保证运放相位裕度满足要求的同时不降低运放的带宽。基于自顶向下的设计流程，利用MATLAB/SIMULINK对调制器进行系统级建模分析，理想情况下调制器的信噪比接近理论计算值。分析连续时间Sigma Delta调制器在电路设计时存在的非理想因素，将非理想因素加入到模型中，建模仿真非理想因素对调制器性能的影响，提出抑制非理想因素的方法，得到每个模块的设计指标。在TSMC 28nm CMOS工艺下实现调制器的电路级设计，并对调制器进行原理图仿真和寄生参数反提后仿真。对运算放大器进行AC/STB仿真，其在200MHz频率处有超过60dB的增益；蒙特卡洛分析每个DAC单元的随机失配在0.9%左右，每个比较器单元的失调电压标准差在2.7mV左右。调制器采用1.8V/1.2V/0.9V/-1V供电，原理图仿真显示，调制器在输入信号带宽达到200MHz的情况下，SNR /SNDR/SFDR分别为77.4dB/74.9dB/78dB；寄生参数反提后仿真显示，在输入信号带宽为160MHz情况下，调制器的SNR/SNDR/SFDR分别为72.1dB/70.2dB/74.6dB。调制器核心部分功耗为144mW，FOM值达到了170fJ/conv。
Continuous-time Sigma Delta modulators are widely used in wireless communication systems. They have unique advantages are in system integration such as their high precision, low input network load, and built-in anti-aliasing filters, compared to other types of analog-to-digital converters. As the speed of wireless communication continues to increase, how to design a wide-bandwidth continuous-time Sigma Delta modulator has become a research hotspot.This paper designs a wide-band continuous-time Sigma Delta modulator that can be applied to 5G communication systems. The modulator adopts a feedforward-feedback hybrid single-loop structure, the oversampling rate is 12.5, the quantizer is four bits, and the loop filter is third-order. The first-order continuous-time noise coupling is added to improve the noise shaping effect of the loop. The loop delay is set to half a clock cycle, and the PI-element method is used to compensate for the loop delay to save power. The internal integrator is an active RC type, the comparator unit in the quantizer consists of a static preventive amplifier and a Strong_ARM type latch, and the feedback DAC is a non-return-to-zero complementary current steering type. To calibrate the random mismatch error between the feedback DAC units, a DAC mismatch front-end calibration circuit based on the successive approximation principle is employed. The operational amplifier in the integrator is a three-stage cascade structure. By means of feedforward compensation, the operational amplifier phase margin is guaranteed to meet the requirements without reducing the bandwidth of the operational amplifier.Based on the top-down design flow, MATLAB/SIMULINK is used to perform system-level modeling analysis of the modulator. Ideally, the signal-to-noise ratio of the modulator is close to the theoretical calculation value. Then, analyze the nonidealities in continuous-time Sigma Delta modulator. Add the nonidealities to the model, model the influence of the nonidealities on the performance of the modulator, and propose a method to suppress the nonidealities. Design indicators for each module.The circuit level design of the modulator is implemented in the TSMC 28nm CMOS process, and verified through both the circuit-level simulation and the parasitic parameter post-simulation. AC/STB simulation of the operational amplifier with more than 60dB gain at 200MHz; Monte Carlo analysis of each DAC unit with a random mismatch of around 0.9%, and each comparator unit's offset voltage standard deviation is nearly 2.7mV. The modulator is powered by 1.8V/1.2V/0.9V/-1V. The circuit-level simulation shows that the SNR/SNDR/ SFDR of the modulator is 77.4dB/74.9dB/78dB when the input signal bandwidth reaches 200MHz. The parasitic parameter post-simulation simulation shows that the SNR/SNDR/SFDR of the modulator is 72.1dB/70.2dB/74.6dB when the input signal bandwidth of 160MHz.The core of the modulator consumes 144mW and the FOM value reaches 170fJ/conv.
