近年来，硅 (Si) 基功率器件性能已经趋于Si材料所决定的理论极限，无法满足电力电子领域对电压、电流和速度等方面快速发展的需求。作为宽禁带半导体材料的碳化硅 (SiC) 具有禁带宽度大、临界击穿电场高和热导率高等优越的材料特性，将使功率器件具有更高的击穿电压、更大的电流密度、更高的开关速度和工作温度。SiC门极可关断晶闸管 (SiC GTO) 是门极电流控制的大功率开关器件，具有高电压、大电流和正向压降低等优点，是高压直流输电，轨道交通等领域的关键器件。虽然国际上已经对SiC GTO进行了多年的研究，取得了不错的进展，但是还存在不少的问题和难点。例如：SiC GTO结构复杂、制造难度大，击穿电压性能受制造工艺因素影响显著；SiC GTO器件长期工作的可靠性仍然受限于SiC材料缺陷和结构；SiC器件封装技术仍然显著影响SiC GTO性能发展和商业化等等。国内的SiC材料技术和器件制造技术的发展等限制了SiC GTO的研究，报道很少。因此，本文对SiC GTO的几项关键技术和器件的研制进行了相关研究：1. 首先确定了用于数值分析研究的物理模型和可靠的模型参数。在此基础上，提出了一种新型带场限环的注入多台阶结终端扩展结构 (MS-GR-JTE)。仿真研究表明，MS-GR-JTE可有效抑制电场集中效应，并且使最优剂量范围得到显著拓宽，有效降低由工艺波动等造成的剂量浮动和SiC/SiO2界面电荷对结构击穿性能的影响。2. 提出了一种新型门极保护侧墙结构 (PSW)。仿真研究表明，PSW可以截断门极边缘载流子通道，抑制门极边缘电流峰值，使门极电流分布更均匀，且不影响SiC GTO开关速度等特性。3. 提出了一种改进型带空间调制缓冲沟槽的刻蚀3台阶结终端结构 (3S-SMBT-JTE)。3S-SMBT-JTE能有效抑制台阶结终端台阶和边缘的电场峰值，拓宽刻蚀工艺窗口，降低SiC/SiO2界面电荷对击穿性能的影响。 4. 基于所提出的3S-SMBT-JTE结构，研制了国内首个超高压SiC GTO器件，并完成封装和动、静态测试。器件正向击穿电压达10 kV，反向击穿电压为-160 V。器件正向导通压降为5.1 V (有源区电流密度为100 A/cm2时)。器件开通上升时间和关断下降时间分别为0.17μs和1.2 μs。

Recently, the performance of silicon based power devices are approaching to their theoretical limits, making it very difficult to meet the needs of higher voltage, higher current density and higher speed in the power applications. As one of the wide band gap semiconductor, 4H-silicon carbide (SiC) has enormous superior material properties, such as: wider band gap, higher critical electric field (EF), higher saturation velocity, higher thermal conductivity, etc, which enables higher breakdown voltage (BV), higher current density, higher speed and operation temperature for the next generation power devices. As high power switch controlled by gate current, the SiC gate turn-off thyristor (SiC GTO) distinguish itself from other SiC devices for the higher BV, larger conducting current and lower forward voltage drop. Hence, SiC GTO is one of the key power device in the application areas of high voltage direct current transmission, rail transport, and so on.Although the research of SiC GTO has been going on for over 20 years with great development of performance, there are still many critical issues and challenges for SiC GTO development. SiC GTO are typically designed with complicated structures, difficult to be fabricated, and demonstrated with BV degradation under the effects of fabrication related factors; The life and reliability of SiC GTO is still limited by material defects and structure issues; Lifetime control technique for SiC material is not mature yet. Lifetime in SiC GTO after control process are not uniform enough, which will limit the switching performance; The packaging technology of SiC power devices still significantly hinder the development and commercialization of SiC GTO, and so on. The research of SiC GTO in China has been longly restrainted by the unmatured SiC material and fabrication techniques, leading to that few of results were reported. This thesis reports our research on the key techniques and design of SiC GTO:1. Suitable physical models for numerical studies have been established with reliable material parameters. Based on that, a new ion-implanted edge termination, referred to as guard-ring assisted multi-step junction termination extension (MS-GR-JTE), has been presented for ultrahigh voltage (UHV) SiC power devices. Simulation studies showed that MS-GR-JTE can effectively suppress the peak EF and EF crowding. Hence, the dose window for achieving superior BV has been greatly extended with wide tolerances to dose variations and SiC/SiO2 interface fixed charges. 2. An new protective side wall (PSW) structure has been presented for SiC GTO. Due to its capability of blocking the way of carries, PSW can suppress the current crowding in the edge of gate area according to simulation results. Under the effect of PSW, the gate current distribution becomes more uniform, while without obviously reducing the switching speed of SiC GTO.3. An improved etched edge termination, referred to as three-step JTE with space modulated buffer trench regions (3S-SMBT-JTE), has been proposed. SMBT can effectively reduce the peak EF and suppress the EF crowding in the edges and corners of 3S-JTE, extend the etching step window for achieving superior BV and reduce the effect of SiC/SiO2 interface fixed charges on BV performance. The 3S-SMBT-JTE has been adopted by the fabricated UHV SiC GTO showing great enhancement of BV performance.4. The UHV SiC GTO with 3S-SMBT-JTE has been demonstrated by us for the first time in China. The wafer and pacakaged SiC GTOs have been tested, respectively, to show their static and dynamic performance. Static high voltage test results show that the SiC GTO can block forward voltage of 10 kV and reverse voltage of -160V respectively. N type (gate) and P type (anode) ohmic contact are 6×10-4 Ω?cm2 and 1×10-2 Ω?cm2, respectively, according to the TLM tests. IV test result shows that the forward voltage drop is around 5.1 V when the current density in active area is 100 A/cm2. The rise time of 0.17 μs and fall time of 1.2 μs were recorded, respectively, in the switching tests.