与非型（NAND）闪存由于其高存储密度、低成本、低功耗等优点，成为目前最重要的非挥发存储元件。传统NAND 闪存在工艺节点发展到15/16nm后，特征尺寸的继续缩小面临着越来越大的挑战，器件物理极限、制造难度提高以及制造成本增加等限制了其进一步发展。三维NAND闪存纵向堆叠闪存器件形成三维阵列，从而实现更高的存储密度，同时保证了闪存的容量、性能和可靠性，成为NAND闪存发展的新方向。三维 NAND闪存继承了传统NAND闪存的设计经验，发展迅速，但在工作机理和结构优化方面依然存在大量待研究工作。本文针对三维NAND闪存中有别于传统NAND闪存的结构，通过以下几个阶段对三维NAND闪存关键技术展开研究：1）工作机理研究。完成多晶硅沟道材料导电特性研究、操作串扰分析及尺寸缩小潜力分析。2）结构优化研究。针对栅介质层、选通管，源漏掺杂，提出改进方案并完成验证工作。3）创新性应用研究。提出了基于三维NAND闪存的人工神经网络硬件结构。取得的主要研究成果包括：1.提出多晶硅沟道漏电流模型：实验发现三维NAND闪存沟道漏电严重及器件间均一性较差问题，提出了基于连续多晶硅晶界的漏电通路模型。此模型合理解释了不同沟道直径三维NAND闪存器件的沟道漏电差异，以及沟道电阻在施加漏端电压后的不稳定现象，可从理论上为多晶硅淀积工艺优化和阵列设计工作提供参考。2.提出高性能三维NAND阵列结构：提出了SiN/SiO2/SiN复合电荷存储层结构，有效提高了闪存器件电荷存储密度及电荷保持能力，并针对三维NAND闪存垂直堆叠闪存器件产生的结构缺陷，提出了二氧化硅单层栅介质层选通管结构、p型衬底n型S/D掺杂结构等改进方案，提高了阵列的编程/擦除速度和可靠性。此方案有效提高了阵列的整体存储性能。3.提出基于三维NAND闪存阵列的人工神经网络结构：创新性地提出了利用NAND闪存阵列实现神经网络功能的硬件结构，此结构利用三维NAND闪存串存储数字突触权重值，并通过分步的闪存读取电流积分操作完成人工神经网络的矩阵乘法运算，具有高集成密度、高精度、高可靠性等优点。

NAND flash memory has become the most important non-volatile memory element, because of its high storage density, low cost, low power consumption, and high performance. After the development of the process node to 15 nm, the shrinking of NAND flash continues to face increasing challenges. Device physical limitations, manufacturing difficulties, and increased manufacturing costs limit its further development. The three-dimensional (3D) NAND flash stacks the flash devices in the vertical direction, thereby realizing higher storage density by using larger-sized memory devices, and at the same time ensuring the capacity, performance, and reliability of the flash memory, becoming the new development direction of NAND flash memories.3D NAND flash inherited the design experience of traditional NAND flash, and developed rapidly. However, there are many differences between 3D NAND flash and traditional NAND flash, thus working mechanism research and structural optimization is meaningful for 3D NAND flash.This paper focuses on the key technologies of 3D NAND flash memory, and carries out research in the following stages: 1) Working mechanism research. Complete polysilicon channel conductivity characteristics research, operational crosstalk analysis and size reduction potential analysis. 2) Structural optimization research. Propose improved scheme on gate dielectric layer, gate tube, source and drain doping, and the verification work was completed. 3) Innovative application research. An artificial neural network hardware structure based on three-dimensional NAND flash memory is proposed.This thesis focuses on the different device and array structure of 3D NAND flash memory from the traditional NAND flash. Research work has been conducted from three aspects: work mechanism research, device and array structure optimization, and artificial neural network application research. The key contributions of this thesis include:1.Leakage current model for polysilicon channel: The serious channel leakage and poor uniformity among the devices of the 3D NAND flash is found in experiment, and a leakage path model based on continuous polysilicon grain boundaries is proposed. This model reasonably explains the channel leakage difference of 3D NAND flash memory devices with different channel diameters, and the instability phenomenon of the channel resistance after applying the drain voltage, which can theoretically provide reference for the optimization of polysilicon deposition process and array design.2.High-performance 3D NAND flash structure: An improved structure of the charge-trapping layer is proposed to improvement of charge storage density and charge retention capability. For the structural defects of 3D NAND flash, optimized structure have been proposed including the SiN/SiO2/SiN charge-trapping layer structure, the SiO2 single-layer gate dielectric selector structure and the p-type substrate with n-type S/D doped structure，and array programming/erase speed and reliability are improved by these optimized structures.3.Artificial neural network based on 3D NAND flash: A innovative structure of artificial neural network based on 3D NAND flash array is proposed. This architecture utilizes NAND flash strings to store digital synaptic weight values, and completes the artificial neural network calculations by multistep flash reading current integrals. This proposal achieves a high-precision, high-reliability artificial neural network structure.