高性能模数转换器(ADC)是基站通讯，军事雷达，高速测量仪器的核心模块，如何同时实现高速度和高精度的性能，一直是学术界和工业界的研究热点。研究该技术，不仅仅有学术意义和商业价值，更具有战略意义。本论文首先调研了当前学术届和工业届出现的高性能模数转换器，总结出了时间交织技术是实现高性能转换器的热门技术。接着调研了各种采样时间偏差的校准方式，并重点关注过零(Zero-Crossing，ZC)检测技术时间偏差校准方法。同时也研究了高性能转换器中的采样开关，参考驱动和校准信号注入的技术。基于上面的研究技术和校准算法，设计一款12bit-2Gsps两通道时间交织流水线型ADC。该ADC主要包括以下特点：(1)采用了一种电平移位式传输门来加强MOS管导通，减小开关导通时电阻的阻值和非线性，尤其克服开关在SS+低温下难以导通的问题；(2)采用了前台校准方式，将VCO产生的校准信号通过源极跟随器的偏置端注入，从而不用断开原始信号，保证信号路径的完整性；(3)采用了一种双电平移位的参考驱动电路，使参考驱动有更大输出摆幅和更快的响应速度；(4) 具有输入幅度限制功能，通过在第一级级电路检测信号，限制余差往后级继续放大，保护薄栅MOS管；(5)具有精细的可变延时线电路，可达到16fs的步进，用于时间偏差模拟纠正；(6)级电路采用冗余技术，实际输出码有14位，用于数字校准。仿真结果表明，在典型温度和工艺下，在804MHz输入，2GHz采样下，SNDR=72.86dB，SFDR=76.47dB，ENOB=11.86bit。尤其是在SS+低温这种条件下，在Fin=86MHz，Fs=2GHz时采用电平移位开关使电路的SNDR，SFDR和ENOB分别从57.12dB，59.73dB，9.20bit提高到77.43dB，78.84dB和12.57bit。本论文最后介绍了一款由具有动态失调校准比较器组成的5bit-Flash-ADC。为了对比，同时设计了一款由不带失调校准的比较器构成的5bit-Flash-ADC。测试结果表明：采用了动态失调校准技术后，静态特性的DNL从1.32LSB减小到0.62LSB，INL从1.20LSB减小到0.55LSB；在输入2.4MHz，采样160MHz下，SNDR从26.25dB提高到29.63dB，SFDR从 35.02dB提高到43.61dB。测试结果表明该校准技术有效。
High-performance analog-to-digital converters (ADCs) are core modules of base station communications, military radar, and high-speed measurement instruments. How to achieve high-speed and high-precision performance at the same time has always been a research hotspot in academia and industry. Researching this technology not only has academic significance and commercial value, but also has strategic significance.This thesis first researches the high-performance analog-to-digital converters appearing in the current industrial and academic sessions. It concludes that time-interleaving technology is the hot technology for high-performance converters. Then, various calibration methods for sampling time-skew are investigated and the Zero-Crossing (ZC) detection technique for time-skew calibration is focused on. At the same time, the sampling switches, reference buffer and calibration signal injection techniques in high performance converters are also researched.Based on the above research techniques and calibration algorithms, a 12bit-2Gsps two-channel time-interleaved pipelined ADC is designed. The ADC mainly includes the following features: (1) A level shifting transmission gate is used to strengthen the conduction of the MOS transistor, and the resistance value and the nonlinearity of the resistance when the switch is turned on are reduced, and in particular it is difficult to overcome the difficulty of the switch at the SS+ low temperature. (2) Using the front-end calibration method, the calibration signal generated by the VCO is injected through the bias source of the source follower, so as not to disconnect the original signal to ensure the integrity of the signal path; (3) A two-level shifting reference buffer circuit allows the reference buffer to have a larger output swing and faster response speed; (4) It has an input amplitude limit function to limit the residual amplifier by detecting the signal in the first stage circuit. Prevent the stage continue to enlarge and protect the thin gate MOS tube; (5)It has a fine variable delay line circuit, can reach 16fs step, used for time deviation analog correction; (6) stage circuit uses redundant technology and the actual output code are 14 bit for digital calibration. The simulation results show that under typical temperature and process conditions, SNDR = 72.86dB, SFDR = 76.47dB, and ENOB = 11.86bit under 804MHz input and 2GHz sampling. Especially in the condition of SS+low temperature, when Fin=86MHz，Fs=2GHz，the level shift switch was used to increase the SNDR, SFDR and ENOB of the circuit from 57.12dB, 59.73dB, and 9.20bit to 77.43dB,78.84dB and 12.57bit, respectively.The paper concludes with a 5bit-Flash-ADC with dynamic offset calibration comparator. For comparison, another 5-bit-Flash-ADC using comparator without offset calibration was designed. The test results show that the static characteristic DNL is reduced from 1.32LSB to 0.62LSB and the INL is reduced from 1.20LSB to 0.55LSB after the dynamic offset calibration technique is applied. At the input of 2.4MHz and the sampling frequency of 160MHz, the SNDR is increased from 26.25dB to 29.63dB, SFDR increased from 35.02dB to 43.61dB. Test results show that the calibration technique is effective.
