伴随着信息技术的不断发展，电子产品的数据处理能力越来越高，人们对于有线和无线传输方式的传输速率的要求也随之增加。由于传统频段无线传输的频谱资源越来越紧张，且其传输速率无法满足人们的需求，60-GHz高频无线传输成为热门的高速无线通信方式。时钟数据恢复电路(CDR)作为高频无线接收机的关键模块，通过对采样时钟的相位进行调节以对准数据中央，消除数据的幅度失真和抖动，并恢复出较低误码率的高质量数据。论文提出了基于Tsmc 65nm CMOS工艺，并应用于60GHz无线收发机的半速率时钟数据恢复电路，首先对常用的时钟数据恢复电路的优缺点进行分析与对比，并选用了相位插值器型CDR结构，综合考虑接收系统需要和环路可靠性，确定了基于相位插值器的半速率CDR结构；其次，介绍了60-GHz无线接收机的结构和CDR在系统中的作用，对Bang-Bang鉴相器作了比较详细的线性化分析，建立了系统模型并对其进行了系统级的功能验证；之后详细介绍了每一个模块的结构，并对其参数进行了讨论；在文章末尾，介绍了系统所需要的仿真环境和版图设计中需要注意的要点，给出了主要模块和环路的后仿结果，并结合理论对结果作了比较详细的分析。论文的设计参数是基于60-GHz无线接收的参数需求，设计中尽可能使用数字电路代替模拟电路，并使用半速率鉴相结构和双沿采样结构，减小了电路的面积和功耗；利用直流失调消除电路平衡数据信号的共模电平，提高了系统稳定性；利用占空比调节电路，使PI调整后的时钟占空比为50%，保证双沿采样的正确性。本文设计了较为完备的仿真方法对系统的性能进行评估，在1.0V的电源电压下，半速率时钟数据恢复电路的I路仿真数据率在1.25Gbps到6.4Gbps之间，总数据率在2.5Gbps到12.8Gbps之间，功耗17.44mW，容忍时钟频偏为100ppm。
With the rapid development of information technology, the data processing ability of electronic products is increasingly higher, so as the demand for the speed of wire and wireless transmission. Due to the resource strain of traditional spectrum wireless transmission and its failure to keep up with the speed need, 60-GHz wireless high frequency transmission becomes the most popular high-speed communication method. As a critical module in 60-GHz receiver, the Clock and Data Recovery （CDR） is responsible for adjusting the sampling clock’s phase to the data, eliminating the data amplitude distortion and jitter, and recovering the high-quality data at a low bit error rate. This thesis presents a half-rate CDR which is based on the Tsmc 65nm CMOS technology and applied to the 60GHz wireless transceiver. First, the Phase Interpolator（PI）structure is adopted after the analysis and comparison among commonly used CDR structures. And comprehensively considering the needs of receiving system and the loop reliability, a half-rate CDR structure based on PI is confirmed. Next, an introduction to the 60-GHz wireless receiver structure and the CDR’s function is given. With a linear analysis on Bang-Bang Phase Detector （BBPD）, the system model is built and verified. Then, a detailed introduction is made for every module, including its structure and parameters. At last, a description of the simulation environment and the key points in the layout design is made. And the post-layout simulation result of main modules and the whole loop is given out and analyzed based on the theory. A relatively complete simulation method is designed in this thesis to estimate the system performance. The design parameters here are based on the need of the 60-GHz wireless receiver, in which analog circuits are replaced by digital circuits as much as possible and half-rate PD and double edge-triggered sampler are used. This has reduced the circuit area and power consumption. Furthermore, the application of DC Offset Cancellation （DCOC） circuit has improved the system stability, and the utilization of Duty Cycle Corrector （DCC） has adjusted the clock duty to 50%, guaranteeing the accuracy of the double edge-triggered sampler. With the supply voltage of 1.0V, I branch of the half-rate CDR operates from 1.25Gbps to 6.4Gbps, and the total data rate is between 2.5Gbps and 12.8Gbps in the consumption of 17.44mW. In this condition, the maximum clock frequency offset tolerance is 100ppm.
