对于高能效的手机片上系统（System on Chip, SOC），动态电压调整（Dynamic Voltage Scaling, DVS）被认为是降低开关转换功率和泄漏功率最有效的方法之一。然而，对于自适应电源，稳定的时钟生成电路的设计很困难。因此，在很多系统中，一个单独的、具有更高电源电压的校准器经常被用来给锁相环（Phase Locked Loop, PLL）供电。在传统的数字锁相环（DPLL）中，单端时间数字转换器（Time to Digital Converter, TDC）的时间分辨率对于电源电压非常敏感，导致PLL的带内噪声和杂散会随着电压变化出现不一致的情况。而1-bit的TDC，也就是二进制鉴相器（BBPD）可以在低电压下实现稳定的相位检测。 BBPD和环形数控振荡器（Ring DCO）同时应用于DPLL中时，可以实现超低电压的设计，但是在小数分频时，又会使带内噪声恶化。数字时间转换器（DTC）往往被用来克服BBPD的非线性，它通过减小BBPD输入处的相位误差来改善PLL的噪声性能。然而，传统的DTC设计是基于反相器和电容的，为了实现大于10-bit的线性度，需要构建反相器和电容阵列，这导致PLL对PVT变化很敏感。本文提出了一种新型的DPLL结构，通过有限冲击响应（FIR）和延时补偿技术的组合，减轻了由于BBPD非线性而引入的相位混叠问题。本设计的输入参考频率为15 MHz（0.6 V）/60 MHz（1 V），输出中心频率为200 MHz（0.6 V）/800 MHz（1 V）。通过采用8-tap FIR和5-bit延时链，DPLL的输出带内相位噪声可以优化近20 dB。此外，本文还对高频环形振荡器进行了研究。通过采用新的增益增强型的Ring VCO结构，PLL在输出频率为13.6 GHz时的带内噪声为-101 dBc/Hz，输入参考时钟频率为850 MHz，功耗为10.3 mW。
Dynamic voltage scaling (DVS) is a viable solution for energy-efficient mobile SOC (System on Chip) design and considered one of the most effective ways in reducing both switching and leakage power consumption. However, robust clock generation is challenging with an adaptive supply. For that reason, a separate regulator with higher supply voltage is often reserved for the phase-locked loop (PLL) in many systems. In the conventional digital intensive PLL, the time resolution of the single-ended TDC (Time to Digital Converter) is highly sensitive to supply voltage, resulting in inconsistent in-band noise and spur performance over supply voltage variation. The 1-bit TDC, namely, the bang-bang phase detector (BBPD) achieves robust phase detection under the low supply. Combined with the ring DCO, the bang-bang DPLL (BB-DPLL) enables an ultra-low voltage design but suffers from serious in-band noise degradation when it operates in a Fractional-N mode.The digital-to-time converter is employed to overcome the nonlinear property of the BBPD by minimizing the phase error at the input of the BBPD. Even though the 1-bit TDC is used, the performance is now limited by the DTC (Digital to Time Converter) linearity since a wide dynamic range of the DTC requires elaborate design efforts to achieve >10-bit linearity. Since the DTC design is based on the inverters and the programmable capacitor array, the DTC performance over PVT variations and supply noise coupling would be a concern.In this thesis, we propose a new DPLL structure, a hybrid finite-impulse response filter and delay compensation are employed to mitigate the phase-folding problem caused by nonlinearity of the BBPD. The DPLL is designed to operate at 800 MHz with the input reference frequency of 60 MHz under 1 V supply and 200 MHz with reference of 15 MHz under 0.6 V. The in-band phase noise of DPLL can be improved by nearly 20 dB by utilizing an 8-tap FIR filter and a 5-bit delay chains.Furthermore, this thesis also shows a gain-boosted two-stage ring oscillator. The PLL consumes 10.3 mW from a 1.2 V supply at 13.6 GHz output with the input reference frequency of 850 MHz. The measured phase noise is -101 dBc/Hz at 10 MHz offset.
