移动多媒体应用如交互游戏对移动应用处理器的性能提出了更高的要求，同时有限的电池能量要求处理器具有更高的能效。近阈值计算能将处理器的能效提高一个数量级。处理器在从近阈值到常压的宽电压范围内调整工作电压，以满足不断变化的工作负荷。为实现近阈值处理器的设计，需要能在近于阈值下稳定工作的标准单元库，单元库的性能和稳定性对处理器有重要影响。本论文对近阈值宽电压标准单元库的设计进行了相关研究，提出了一种工艺扰动下的单元尺寸设计方法。基于SMIC 40nm 1P10M工艺设计了单元的版图和单元延时测试电路，生成了支持EDA设计流程的单元库文件。使用基准电路对近阈值库进行了评估验证。最后采用近阈值单元库实现了安全哈希算法处理器，该处理器采用近阈值库进行了仿真，综合和后端布局布线，完成了40nm工艺下的版图设计，已经投片待测试。具体工作如下：（1）近阈值下的工艺扰动是最大的挑战，论文首先分析了工艺扰动对单元延迟，噪声容限的影响，并研究了单元延迟及噪声容限建模测试电路。在此基础上提出了一种工艺扰动下的单元尺寸设计方法，根据该方法设计的单元延迟在近阈值0.6V下比商用单元库降低了4.8%-16.4%，噪声容限的均值提高了3.9%-6.6%。基于SMIC 40nm工艺完成了单元测试电路和版图设计。（2）完成了库特征化，生成了近阈值库文件。采用ISCAS’89和ITC’99基准电路套件进行了逻辑综合。与商用标准单元库相比，在0.6V下基准电路的速度提高了4.5%-16.9%，功耗降低了6.7%至22.3%。（3）采用本论文设计的近阈值单元库实现了安全哈希算法（SHA）处理器。完成了SHA处理器的仿真，综合以及后端布局布线。采用SMIC 40nm 1P10M工艺完成了SHA处理器的版图。通过SHA处理器前端综合到后端布线的过程，验证了近阈值单元库对数字设计流程的支持。该SHA处理器已经投片待测试。
Multimedia applications such as interactive games posed stringent performance requirements for microprocessors using in mobile application. Meanwhile, the power of microprocessor needs to be lowered in standby mode or other situation for longer battery life. One solution to meet varying performance requirement is near threshold computing. Near-threshold computing brings the promise of an order of magnitude improvement in energy efficiency over the current generation of microprocessors. To enable the processer working at near threshold voltage for better energy efficiency, a digital standard cell library optimized for wide voltage range is necessary for better performance and reliability of microprocessor..In this paper, the design methodology of developing a standard cell library specific for 0.6V operation in 40nm CMOS technology is presented. An optimized method of sizing sub-threshold cells considering process variation is stated. The library for wide voltage operation is designed and key considerations leading to better cell performance over 0.6V-to-1.1V voltage range are demonstrated. Then the library is characterized and validated with ISCAS’89 and ITC’99 benchmark circuits. Comparison results on power and performance between our library and the foundry-provided one are shown. The 40nm 0.6V standard cell library is used in the SHA processor. Utilizing the standard cell library, the SHA accelerator core scales as synthesized from better performance at 1.1V down to lower power at 0.6V.(1) At near-threshold voltage, process variation remains the biggest challenge. This paper analyzes cell delay and noise margin variation. Then an optimized method of sizing sub-threshold cells considering process variation is stated. Using this method, unit delay at near threshold 0.6V decreased 4.8% -16.4%, and the mean noise margin improved by 3.9 % -6.6% compared with the commercial library. Based on SMIC 40nm process cells are designed and test circuit layout are drawn. (2) The cell library is characterized at 0.6V and 1.1V corners for synthesis at near threshold and normal voltage. Four benchmark circuits from ISCAS’89 and ITC’99 benchmark suite were selected to test library performance when synthesizing practical circuit. The benchmark circuits were synthesized using our library and foundry provided one. Evaluation with benchmark circuits show 4.5%-6.9% speed improvement and 6.7%-22.3% less power consumption synthesized at 0.6V compared with the foundry-provided one.(3) Our near-threshold library is utilized in the implementation of a SHA IP core. The SHA IP is a SHA algorithm accelerator. It is synthesized at 0.54V 125℃ SS corner with corresponding library file. The clock frequency is 5M. Evaluation with SHA core show around 80% less power consumption synthesized at 0.6V compared with 1.1V. The SHA core are taped out and future test on silicon is under-going.
