短距离无线通信系统在近年来发展迅速，超宽带（UWB）通信系统取代传统窄带通信系统在商业和研究领域受到极大关注。UWB信号因其丰富的可用带宽可以提供高数据率，同时使用实时短脉冲以达到极低功耗。脉冲无线电超宽带（IR-UWB）技术在设计上能实现相对较低的复杂度和低功耗，因此广泛被运用于短距离无线应用，包括个人区域网络、低功率无线传感器网络和无线体域网等领域。IR-UWB灵活的带宽也可用于精确定位系统和专用的高数据率通信链路中。 基带多相位时钟生成电路在IR-UWB收发机系统中起到重要作用：在发射机中，它可产生多相位时钟，用来合成数字脉冲包络；在接收机中，它可利用多相位时钟进行码元级别（symbol-level）的同步。本论文旨在设计一款用于IR-UWB收发机的多相位时钟生成器，可提供10相位2G Hz的基带时钟信号。本文所设计的多相位时钟生成器通过分析锁相环（PLL）和延时锁定环（DLL）的结构共性，创造性地提出了一种可配置的PLL/DLL双模时钟生成电路结构，使其可分别在PLL和DLL两种不同的模式下工作。PLL模式可提供抑制时钟漂移，DLL环路 稳定性强，并可以通过改变输入参考频率来改变系统的数据率。可配置的PLL/DLL双模多相位时钟生成电路对于IR-UWB收发机系统的工作有着极其重要的作用。本文分析了负载不匹配时造成的相位不均衡问题，为了多相位时钟生成器在PLL和DLL模式下都能正常工作并产生均衡相位的时钟信号，提出了一种全匹配的压控振荡器/压控延时线（VCO/VCDL）双模可配置电路。多相位时钟生成器基于65nm CMOS工艺设计实现，有效面积为0.03mm2。根据测试结果，PLL模式工作时输出相位噪声为-85.04dBc/Hz @ 1MHz，参考杂散功率为-46.89dBc。给定1V供电电压，电路总功耗在PLL模式工作时为2.1mW，DLL模式工作时为2.4mW。该多相位时钟生成电路可为超宽带收发机提供基带时钟信号，同时也提供了脉冲调制信号，使超宽带收发机系统能更好地工作。该芯片为目前SOC芯片中两种最主流的时钟生成电路的结合提供了一种解决方案，有很大的研究意义和潜能。在上述研究基础上，本文还提出了一种基于??调制的全数字LDO，可以为时钟生成器提供低纹波的片内供电电源，改善VCO的噪声性能。该全数字LDO基于180 nm CMOS工艺设计实现。
With the recent development of short-range wireless communication systems, the ultra-wideband (UWB) transceiver system has received great attention as an alternative to narrowband systems in the area of research. UWB signals not only supports high data rates with wide channel bandwidth but also offers low power with the use of narrow pulses in time domain. The impulse radio UWB (IR-UWB) system can be designed with relatively low-complexity and low power consumption, and it has been widely used in short-range wireless applications including personal-area-networks, low-power sensor networks, and wireless body-area-networks. Because of the bandwidths that can be achieved with IR-UWB radios, they are also used in precise location systems and for dedicated high-date rate communication links.A baseband multiphase clock generation circuit plays an important role in the IR-UWB transceiver system. It can generate multiphase clock for the synthesis of a digital pulse envelope in a transmitter, and use multiphase clock to realize the synchronization of symbol-level. This thesis aims to design a multiphase clock generation circuit for the IR-UWB transceiver which provides 10 phase baseband clock signals with the frequency of 2GHz. By analyzing the common characters of the phase-locked loop (PLL) and the delay-locked loop (DLL), this thesis proposes a dual-mode reconfigurable PLL/DLL clock generation circuit structure, which can work either in the PLL mode or in the DLL mode. The PLL prevents the clock drift, while the DLL offers better loop stability. The data rate of the system can be controlled by changing the input reference frequency. Therefore, the proposed reconfigurable PLL/DLL dual-mode multiphase clock generation system is useful for the IR-UWB transceiver system.This thesis analyzes the problem that load mismatch could bring, and proposes a fully-matched voltage-controlled oscillator (VCO) and a voltage-controlled delay line (VCDL) dual-mode reconfigurable circuit in order to maintain proper operation of both the PLL mode and the DLL mode. The multiphase clock generation system is fabricated in 65nm COMS process, and the active area is 0.03mm2. According to the testing result, the output phase noise is -85.04dBc/Hz @1MHz and the reference spur is -46.89dBc in the PLL mode. The power consumption is 2.1mW in the PLL mode and 2.4mW in the DLL mode while the supply voltage is 1V. This multiphase clock generation system can supply baseband clock signals and impulse modulated signals for the UWB transceiver system, making the UWB transceiver system more flexible.Based on the research of clock generation, A ??modulated all digital LDO is proposed in this thesis. It works as the internal supply voltage of the VCO and improves the noise performance. This DLDO is fabricated in 180nm CMOS process. Testing results show that the VCO performance can be improved with the proposed LDO.
