石墨烯因其优越的电学性质成为近年备受瞩目的纳米电子材料。本文参考了学术界最新的科研成果，对石墨烯的射频电子学应用进行了较为系统的研究。 首先，围绕载流子迁移率和栅控展开讨论，它们是石墨烯场效应管性能的决定性因素。表面修饰方面的研究发现多种自组装分子层（SAM）具有提高石墨烯载流子迁移率的作用，以苯环为终端的SAM尤其提升载流子迁移率超过三倍。半悬空沟道的石墨烯场效应管，作为一种新结构，通过将沟道部分撑起，获得超过40000 cm2v-1s-1的载流子迁移率。针对栅控问题，开发了埋栅技术从而避免在石墨烯上生长栅介质的难题，获得等效氧化层厚度约3 nm的栅介质。 随后，制备了栅长在200 nm~1.5 μm的射频场效应管，最高获得截止频率fT=33.7 GHz和最高震荡频率fmax=36.5 GHz，由于低电阻埋栅的引入，fmax为目前最高水平之一。作为对器件工艺的反馈，建立了石墨烯场效应管小信号模型。为进一步获得在电路仿真上的便捷性，参考已有工作建立起完备的石墨烯场效应管大信号模型，并以Verilog-A语言实现。 在电路集成方面，充分考虑石墨烯的二维材料性质，开发了一套无源元件在先，有源器件在后的倒置集成工艺。利用CMOS后段工艺完成无源元件和石墨烯场效应管埋栅结构，随后脱离CMOS工艺线进行石墨烯转移和后续器件制备。该方法使石墨烯免受后段工艺沾污，同时最大程度的利用现有成熟的CMOS技术。 将倒置集成工艺和器件建模的工作运用在三种石墨烯电路：1）石墨烯倍频器。该电路集成了一个石墨烯场效应管和一个片上电感，获得-26 dB转换增益和4 GHz带宽，为同类工作最好水平，视其为倒置集成工艺综合优势的体现。2）石墨烯混频。制备了单管阻性混频器和基于这一结构的四管双平衡混频器。后者将三阶交调点提高至21 dBm，并获得纯净的输出频谱。该电路的集成度也是目前最高的，单片集成了四个石墨烯场效应管，四个片上螺旋电感和四个MIM电容。3）石墨烯分布式放大器。该电路以传输线的方式将多个石墨烯场效应管跨导叠加从而获得增益，为克服石墨烯难以实现放大的固有缺点提供了一种行之有效的解决方案。应用大信号模型和场效应管实测数据分别进行了电路仿真，获得优异的仿真结果。
Graphene, as a “miracle material”, is of great interest in recent years. This thesis is a systematic study on graphene’s applicaton in RF electronics. In the first beginning, two significant factors in graphene field-effect transistors (GFETs), the carrier mobility and gate dielectrics, were investigated. Several kinds of self-assembled monolayers (SAMs) were used to modify the graphene interface, most of which improved the graphene’s carrier mobility. Phenyl-terminated SAM, in particular, increased the carrier mobility by more than three times. The graphene channel was suspended in part in a new GFET design, which generated a carrier mobility of more than 40000 cm2v-1s-1. Buried gate structures were then studied to avoid depositing gate dielectrics on the inert surface of graphene. Gate dielectric with thickness 3 nm in EOT was achieved. Afterwards, GFETs with gate lengths from 200 nm to 1.5 μm were fabricated. fT=33.7 GHz and fmax=36.5 GHz were achieved. fmax is among the highest in literature, and is attributed to the low resistance of the buried gate. Based on these results, a small-signal model was built as a feedback to the device fabcrication processes. Furthermore, a compressive large-signal model was established and implemented in Verilog-A language. The large-signal model provides convenience in circuit design. As for circuit integration, we proposed a “passive-first-active-last” integration scheme, as what we call “inverted process”. CMOS back-end-of-line (BEOL) technology was used to fabricate on-chip passive components, interconnects and buried gate structures. Then, graphene was transferred followed by GFET fabrication processes. In this method, graphene was kept away from BEOL process contaminations, and CMOS techniques were utilized to maximum extend. Based on the inverted process and the large-signal device model, we proposed three types of graphene circuits. 1) Graphene frequency multiplier. The circuit integrated a GFET and an on-chip spiral inductor. It achieved a conversion gain of -26 dB and a bandwidth of 4 GHz, and is listed as one of the best works in graphene frequency multipliers. 2) Mixer. Both the single-GFET resistive mixer and the cross-coupled four-GFET double-balanced mixer were fabricated. The latter achieved third-order intercept (IIP3) up to 21 dBm and generated a pure output spectrum. The integration level is among the highest in literature. The chip integrated four GFETs, four on-chip inductors and four MIM capacitors. 3) Graphene distributed amplifier. Transmission lines were employed to combine multiple GFETs in phase to generated desirable gains. Both the large-signal model and S-paremeter measurement results were used in the circuit simulations. This work provides a constructive solution to overcome graphene’s longstanding weakness in generating gains.
