相比经典的发射机结构，极坐标发射机采用相位、幅度调制相结合的方式简化了发射机的整体构架，节省了面积和功耗。相位调制器是极坐标发射机的关键组成之一，用于产生恒定包络的相位调制信号，其工作状态直接影响到整体发射机的性能。本论文中主要针对基于锁相环的线性相位调制开展研究，分析了相位调制器中的非理想因素以及解决方案，并流片验证了系统的可行性。首先介绍?锁相环的工作原理，对单点预补偿和两点调制的优缺点进行对比，确定两点调制为本论文主要研究的调制方式。进而对两点调制进行了行为级建模，分析了非理想因素的起因和影响，简要介绍目前已有文献的解决方案。其次提出基于混合型锁相环的相位调制器结构，通过对模拟和数字方案的综合考虑，实现了性能、复杂度、设计成本的良好折中。同时混合型的电路结构减小了电荷泵的动态范围，提高了系统的线性度，进而减小了线性电荷泵的设计难度。第三，提出了内置FIR滤波器的1-bit DCO调制结构，极大的减弱了两点调制对DCO非线性的敏感度，提高了调制器的线性度。第四，低通调制路径采用了混合型FIR滤波的技术，提高系统的线性度：一方面降低?调制器的量化噪声影响，另一方面提高了电荷泵的线性度，进而优化调制器的性能。采用TSMC 65nm CMOS工艺实现了1.8GHz 270kb/s GMSK数字相位调制。设计基于混合环路的架构，优化了杂散性能，同时实现了带宽的线性控制。当采用270kb/s GMSK调制时，调制器的频谱满足GSM标准的频谱掩膜，并且在400kHz频偏处有3.5dB的噪声裕量。采用TSMC 65nm CMOS工艺实现了1.8GHz 1.08Mb/s GMSK和GFSK数字相位调制，同时采用混合环路、1-bit DCO调制、混合型FIR滤波的技术。在913.2MHz输出频率处，1.08Mb/s的GMSK和GFSK调制对应的RMS EVM分别为1.78%和1.96%，实现了线性的相位调制。通过测试结果说明了所提出了相位调制器适用于低功耗、低电压、低复杂度、高线性度的系统设计。

Compared with conventional transmitters, the polar transmitter consumes less power and area without requiring mixers, digital-to-analog converters (DACs) and low-pass-filters (LPFs). In addition, by utilizing phase and amplifier modulation individually, the power amplifier is able to work in the switch mode which improves the power efficiency a lot. The phase modulator is one of the key blocks in the transmitter and any non-ideal effects in the modulator will degrade the system performance directly. This dissertation is focusing on the linear phase modulator design based on the phase-locked loop (PLL) architecture. By analyzing the non-ideal effects in the phase modulation, several techniques are proposed to improve the performance. The proposed architecture is also implemented in CMOS for the system verification. Firstly, the principle of the ? PLL is presented, including the working mechanism and filtering characteristic, which are the basic of the phase modulation. And then, the phase modulations with one-point and two-point methods are compared. The two-point modulation is chosen in this dissertation which is more suitable for the high data rate modulation. By modeling the two-point modulation, the non-ideal effects are analyzed and the recent researches on these issues are studied. In this work, three techniques are proposed to improve the performance of the two-point phase modulation.The hybrid-loop architecture is proposed for the phase modulation by employing a semi-digital ? PLL. The semi-digital ? PLL provides linear phase tracking and low-complexity design, while offering technology scalability and digital-assisted calibration capability without complex time-to-digital converter (TDC) design.A 1-bit high-pass modulation with FIR finite impulse response (FIR) filtering is proposed. The use of the dedicated 1-bit high-pass modulation path mitigates the nonlinearity problem of the digital controlled oscillator (DCO) gain in the two-point modulator design, which can substantially simplify the two-point modulator architecture while achieving good linearity. In addition, the hybrid FIR filtering method is employed for the low-pass modulation path to enhance linearity and reduce high frequency quantization noise.The hybrid-loop phase modulator with TDC-less semi-digital??PLL is implemented in 65 nm CMOS, consuming a 6.9 mW from a 1 V supply. When the 270.833 kb/s GMSK modulation is applied, the proposed hybrid modulator meets the spectrum mask requirement for GSM standards with 3.5 dB margin at 400 kHz offset frequency. A 1.8 GHz 1.08 Mb/s GMSK/GFSK hybrid-loop two-point modulator based on the TDC-less semi-digital??PLL has been implemented in 65 nm CMOS. At the divide-by-2 output frequency of 913.2 MHz, the error-vector-magnitude (EVM) values of 1.79% and 1.63% are achieved with 1.08 Mb/s and 270 kb/s GMSK modulation respectively. When the 1.08 Mb/s GFSK modulation is performed with the same PLL parameters, the EVM value of 1.96% is achieved. The experimental results show that the proposed hybrid-loop architecture offers an alternative way of realizing digital modulation while avoiding the complicated design effort for the high performance TDC. The digital FIR filtering and the hybrid FIR filtering methods employed for the high-pass and low-pass modulation paths are shown to be useful to improve the modulation linearity and reduce the coupling effect. The testing results also prove that the use of the 1-bit high-pass modulation path achieves good linearity without complex calibration blocks.