为了增加晶体管器件的工作电压，横向扩散金属氧化物半导体（Laterally Diffused MOS, 缩写为LDMOS）晶体管广泛的应用于BCD（Bipolar-CMOS-DMOS）工艺和CMOS工艺。和标准CMOS工艺兼容的LDMOS在非挥发性存储器（Non-Volatile Memories, 缩写为NVM）、射频识别（Radio Frequency Identification，缩写为RFID）、液晶显示器（Liquid Crystal Display, 缩写为 LCD）、以及电源管理电路等方面有非常广阔的应用。进入深亚微米阶段，采用CMOS标准工艺晶体管器件的平均工作电压降低了，氧化层变薄了。为了使LDMOS器件在标准CMOS工艺下能够达到性能要求，需要通过新的器件结构设计来增加LDMOS器件的击穿电压（BVdss）和在高电压区域的稳定性。为了达到这个目的，研究人员提出了与标准CMOS工艺兼容的N沟道缓变结LDMOS晶体管。因为缓变结是通过重复利用N型晶体管的掩膜板掺杂实现的，其器件不需要任何工艺改动或增加掩模版，是完全兼容于标准CMOS工艺的，具有很好的应用前景。本论文的研究目标是在130nm标准CMOS工艺下，如何优化LDMOS器件的结构设计，实现高的击穿电压，提高器件在高电压区域的稳定性。在本论文中，通过参数相关性研究得知减小Lw（栅氧化层和N阱之间的重叠区域），可以显著增加器件的击穿电压。通过TCAD仿真软件，进行了Lsub和Lw的优化，使得击穿电压增加到了29V，比早期结构的击穿电压提高了大约45%。本论文研究发现热载流子注入（Hot-carrier-induction，缩写为HCI）导致缓变结LDMOS电阻降低会导致Lsub增加。本文发现采用silicide blocking的工艺技术可以解决Lw = 0器件导通电阻波动更大的问题。最后对于缓变结LDMOS的整体尺寸和具体导通电阻(Specific on-resistance, 缩写为Rsp)进行了优化。采用本文的方法对器件的整体尺寸优化后，不会对器件的性能造成影响。
LDMOS (Laterally Diffused MOS) transistor has been used extensively in BCD (Bipolar-CMOS-DMOS) process and CMOS process to increase the operation range of a transistor. CMOS process compatible LDMOS is widely applicable to NVM (Non-Volatile Memories), RFID (Radio Frequency Identification), LCD (Liquid Crystal Display) driver, and power management circuits. As getting into the deep submicron regime, the average operation range of a transistor fabricated in standard CMOS process is decreased, and the oxide thickness becomes thinner. In order to make the LDMOS device in CMOS process to meet the requirement of the performance, it is necessary to increase BVdss of the LDMOS device by designing a new device structure and its stability in the high voltage region. For this purpose, N-channel Graded-Junction LDMOS was proposed previously. Since Graded-Junction can be implemented using n-type native transistor doping, the device is fully compatible with CMOS process, and doesn’t require any modification of the process or an addition of mask(s), having an entirely applicable background. The goal of this dissertation is under 130nm standard CMOS process to optimize the design of the LDMOS transistor structure, to achieve a high breakdown voltage, and to increase the reliability of the device in the high voltage range. Here, through the investigation on parametric dependences, it is figured out that reducing Lw (Overlapped region between gate oxide and N-well) has an important role in increasing BVdss of a GJ-LDMOS device. Through a TCAD simulation, Lsub and Lw is optimized to achieve BVdss of 29V, which is about 45% improvement of a previous structure. It is found that HCI (Hot-carrier-injection) induced on-resistance degradation in GJ-LDMOS can be improved as increasing Lsub. It is found that by using a silicide blocking process technique, a problem of the severe HCI degradation in Lw = 0 device can be greatly enhanced. Finally, the minimization of GJ-LDMOS is discussed to reduce the specific on-resistance. The performance is still remained as same with the proposed method.
