随着工艺尺寸的不断降低和对集成电路功耗要求的不断提高，传统模拟锁相环（PLL）的设计变得越来越困难。新的应用要求锁相环具有更好的PVT鲁棒性和可编程性能，以及在工艺更新时便捷的移植能力，因此全数字锁相环（ADPLL）正日益成为研究的热点。本文首先讨论了现有的ADPLL结构，指出时间数字转化器（TDC）是引发ADPLL输出杂散和相噪恶化的重要原因。研究了TDC的工作原理和性能衡量指标，并调研了多种TDC结构，由于DLL （延时锁相环）TDC具有良好的PVT鲁棒性、较好的线性度、动态可调的分辨率和方便的杂散打散方式而被选为本设计所采用的TDC结构。本文通过行为级仿真验证了基于ΔΣ ADDLL（全数字延时锁相环）TDC的ADPLL在系统上的可行性。采用了基于动态改变延时控制字的方式而非延时链输出相位选择的方式使用ΔΣ模块，并且证明在使能ΔΣ模块后，ADPLL的输出频谱杂散可以得到较为明显的抑制。针对ADDLL TDC应用于ADPLL的特殊性，深入探讨了相位误差发生突发性变化的机理，提出的相位误差补偿模块可有效消除该突发性变化。本文对ADPLL关键模块的电路实现进行了细致的分析。提出了一种改进的数控延时链，该延时链可实现延时控制电流与延时控制字之间的近似倒数关系，从而可以使延时链的线性度和延时调节范围获得较大的提升。采用了经典的LC DCO结构，可实现2.0-2.5GHz的频率调节范围。本文所述芯片已使用0.18?m CMOS工艺流片并测试完毕，芯片有源区面积为6.4mm2，功耗为12.8mA，其中TDC功耗为2.7mA。测试结果表明：基于ΔΣ ADDLL TDC的ADPLL可以正常工作，且使能ΔΣ功能后，其杂散抑制约为15dB。测试结果证实了ΔΣ ADDLL TDC应用于ADPLL的可行性和有效性，为后续的研究提供了参考。

With the technology scaling and the tight requirement of power dissipation of integrated circuit, the design of the traditional analog phase-locked loop (PLL) becomes more challenging than ever. Since recent applications demand the PLL has good PVT robustness, programmability and reliable design migration with the advanced CMOS technology, all digital phase-locked loop (ADPLL) is now a research hotspot.This paper first discusses the existing structures of the ADPLL, pointing out that the time-to-digital converter (TDC) is one of the most critical block for the phase noise and spur performance of the ADPLL. Operation principle and performance factors of the TDC and various architectures are studied. A delay-locked loop (DLL) based TDC is adopted in this design for its PVT robustness, good linearity, dynamically adjustable resolution and spur reduction by dithering. Based on the behavioral simulation, the feasibility of using a ΔΣ ADDLL（all digital delay-locked loop）based TDC for the ADPLL is verified in this thesis. The ΔΣ module operates based on the dynamic change of a digital delay control word rather than choosing output phases in the delay chain, the spurs of ADPLL output spectrum can be well suppressed when the ΔΣ module is enabled. By considering the the ΔΣ ADDLL effect on the ADPLL performance, the mechanism of sudden changes of the phase error is deeply discussed, and a phase error compensation module is proposed, which can effectively eliminate the sudden phase error change.The circuit implementation of the key modules is described in detail. An improved digital control delay line realizes approximately inverse relationship between the delay control current and the digital control word, thus achieving good improvement of the linearity and delay range. A conventional LC digitally-controlled oscillator (DCO) is designed and achieves the tuning range of 2.0-2.5 GHz.The chip described in this paper has been taped out in 0.18?m CMOS. The core area is 6.4 mm2. The ADPLL consumes 12.8 mA from a 1.8V supply, where the TDC consumes 2.7 mA. Testing results show that the ΔΣ ADDLL TDC based ADPLL works properly, achieving the spur suppression of nearly 15dB when the ΔΣ modulator is enabled. In this work, the feasibility and the effectiveness of the proposed ΔΣ ADDLL TDC based ADPLL is verified in hardware, which can provide references for subsequent researches.