近几年来，无线通信产业已经成为世界上发展最快的领域，无线通信领域已经深入人类生活的方方面面。同时，随着人类生活水平的日益提高，人类对医疗的需求日益增加，医疗人员的人数的增长已经跟不上社会的需求。所以，移动医疗已经成为无线通信产业里比较热门的领域。在无线体域网的几种物理实现中，超宽带（UWB --Ultra-Wide Band）相比于传统窄带通信具有功耗低、时间精度高、系统复杂度低等优点，适用于探测人体生命体征的移动雷达中。在超宽带雷达中，脉冲超宽带(IR-UWB)雷达比连续波超宽带（FM-CW-UWB）雷达功率更低，精度更高，所以非常适用于无线体域网。在传统的脉冲超宽带雷达中，发射信号的频谱利用率不高，同时增加了接收机的设计难度。采用跳频结构可以提高发射信号的频谱利用率，降低接收机功耗和接收机设计难度。同时使用多比特量化的ΔΣ时间数字转换器可以降低“过界”问题在输出频谱上产生的谐波，同时还能提高系统精度。本论文主要贡献在于设计并实现了跳频脉冲超宽带雷达中的跳频发射机和接受机中的二阶多比特ΔΣ时间数字转换器两个重要的电路模块。为了减轻接收机的设计负担，本雷达的发射机采用闭环结构。通过对锁相环结构和模块电路的特殊设计，可以使锁相环快速地锁定在几个频点上。同时采取脉冲整形技术，使发射脉冲的形状类似二阶脉冲，具有较高的带宽利用率和较低的带外泄漏。同时采用BPSK调制以平滑频谱。这种发射机可以发送精确地载波信号和良好的脉冲整形。本文同时给出了整体电路仿真结果。对于本文提出的新的高阶多比特ΔΣ时间数字转换器，在整体上采用单环结构以减小电路非理想因素对调制器性能的影响。同时利用行为及仿真，优化了调制器参数。采取了“电容分裂”技术以减小D/A转换器非线性带来的性能下降。同时，为扩大时间数字转换器的捕捉范围，本文给出了相位跟踪器的电路结构以及跟踪算法。最后还分析了电路中各种非理想因素对时间数字转换器的精度的影响，并给出了整体电路仿真结果和性能对比。本论文中实现的模块均已在TSMC65nm标准CMOS工艺下流片，本文给出了芯片显微照片。
Nowadays, wireless communication has been one of most “hot” research field in the world, and it also places significant influences on human’s life. Meanwhile, along with the development of economics, people tend to pay more attention on medical service. There is a huge gap between the growing demand for better medical service and the slowly increasing amount of doctors and nurses. Therefore, mobile medical service will be huge market in the future.Among the physical implementations in the protocol of IEEE 802.15.6, UWB (Ultra-Wide Band) is a most competitive choice for simple system architectures, low power consumption and high resolution in time domain against conventional narrowband communication system. Compared to FW-CW-UWB, IR-UWB has even smaller power consumption and higher time-resolution. Therefore, IR-UWB is more appropriate to WBAN application.In the conventional architectures, the transmitter couldn’t utilize the frequency band effectively, and also increase the design burden in receiver. Using the concept of frequency-hopping will relieve the design burden and power consumption in receiver and boost the efficiency of frequency band. At the same time, utilizing multi-bit ΔΣ TDC (Time-to-Digital Converter), we can decrease the distortion in the output of Radar due to “cross boundary” issue, which also boost the resolution of TDC. This thesis mainly contributions is two critical building blocks-–closed-loop transmitter and multi-stage multi-bit ΔΣTDC with high resolution for this Radar system. To calibrate the carrier frequency with receiver, this transmitter utilizes a PLL (Phase Lock Loop) to generate carrier frequency with low phase noise. This PLL can lock up quickly in several frequencies. Also the pulse shaping technique is used to generates pulse approximately to second-order pulse to gain a low out-band Emission and high frequency-utilizing ratio. We also use BPSK to do the “scrambling”, which make the spectrum more smooth. The top-level simulation is given in this thesis.For the second-order multi-bit TDC, this thesis use “single loop” architecture to avoid the negative influence from non-ideal element in the circuits, and the parameters are also optimized by behavior-level simulations. The TDC also make use of “capacitor splitting” technique to reduce the non-linearty from D/A converters. The phase rotator is given to enlarge the effective range for TDC. This thesis also analyzes the negative influence non-ideal placed on the circuits. The thesis presents the top-level simulation results and the performance comparisions.All the building blocks presents in this thesis has been taped out under the process in TSMC 65nm Standard CMOS.
