自2003年起，人们对FM-UWB收发机的研究投入很大热情。但截至目前，它的众多关键技术仍有这样或那样的不足，在系统级上也缺乏行之有效的功耗优化方法。本论文针对FM-UWB收发机已有设计的不足，提出了自己独特的技术解决方案， 主要完成了下述研究工作：阐述了FM-UWB收发机的工作原理，指出了收发机的设计难点。回顾了现有的技术解决方案，讨论了它们的不足之处。针对现有工作的不足和收发机的设计难点，采用了全新的发射机架构和改进的接收机实现。首次从系统级上考虑超宽带调频收发机的功耗优化，提出数据边沿检测触发的动态功耗优化方法，实测表明系统功耗节省53%。在发射机中引入数据边沿跳变检测逻辑，在接收机中引入包络检波控制电路。收发机的射频大电流模块仅仅工作在数据发生0/1或1/0跳变的半比特周期内，而接收端又不丢失数据。提出了超宽带调频发射机的新架构，包括基于多相小数分频型锁相环的子载波生成，和基于亚连续型锁频环的射频中心频率校正。与已有架构相比，支持更高的数据率，消除了开关噪声，提高了系统的可配置性，设计更简单，易于CMOS工艺集成。提出了多相三角波、方波发生器的新结构。四相结构用闭环方式实现，区别于传统的开环结构，取得了很好的相位匹配；而基于所能查阅的已有文献，八相闭环结构是首次公开讨论的。提出了射频VCO的双通路设计思想：伪差分开环调频通路提高了频率调制的线性度；单端闭环校正通路确保了射频中心频率的稳定。调制和校正同时进行，不同于已有的先闭环校正后开环调制的思想。提出了基于模拟相位内插型延迟线的射频FM解调器。与已有的借助滤波器群延时的实现相比，模拟延时精确可调，利于解调器带宽和灵敏度的优化，设计实现简单，鲁棒性强，易于CMOS工艺集成。本论文使用UMC 180nm CMOS工艺，设计了多款FM-UWB发射机和收发机芯片。验证了上述的技术解决方案，实现了子载波调制因子、射频中心频率和超宽带带宽的可配置设计。
From 2003 on, people focus more and more on FM-UWB transceiver. However, to the present, it has still many technique disadvantages and is lack of system-level power optimization method. To solve the existing design deficiencies, the main research items and achievements of this dissertation are as follow:The existing implementation techniques are reviewed and their deficiencies are clarified. The principle of FM-UWB transceiver is presented with design difficulties focused on. Considering the existing technique deficiencies and design difficulties, innovative transmitter architecture and optimized receiver implementation are proposed.System-level dynamic power optimization method based on data edge detection and trigger is proposed for the first time, the experimental results show that 53% power saving is achieved. Data transition detection logic is included in the transmitter and envelope detector is used in the receiver. The RF current-starving modules of the transceiver are only active for a half-bit period during data transition, and the receiver will not lose data information by adding some simple digital logic.Innovative FM-UWB transmitter architecture is proposed, including multi-phase fractional-N phase-locked loop (PLL) based subcarrier generation, and quasi-continuous frequency-locked loop (FLL) based RF center frequency calibration. The proposed architecture is fit for high data rate application and CMOS fabrication, eliminates switch noise and improves system reconfiguration, as well as simplies design implementation.Innovative architecture of multi-phase triangular / square waveform generator is proposed. Different from conventional open-loop mode, Four-phase architecture based on closed-loop mode achieves good phase match. Eight-phase architecture is given for the first time based on the published literature.Dual-path RF voltage-controlled oscillator (VCO) is proposed. Pseudo differential open-loop frequency modulated path improves modulation linearity, and single-ended closed-loop calibration path ensures RF center frequency stable. Different from the existing first-calibration later-modulation mode, the proposed architecture conducts modulation and calibration simultaneously.Analog phase-interpolator delay line based RF FM demodulator with widely tunable delay is proposed. The presented architecture fit for CMOS fabrication, has an analog delay tuned finely and continuously with simple implementation, which benefits demodulator performance optimization in RF bandwidth and sensitivity, and ensures high robustness. FM-UWB transmitters and transceiver are implemented in UMC 180nm CMOS to verify the proposed techniques and methods above. The reconfiguration design on subcarrier modulation index, RF center frequency and UWB bandwidth is achieved.
