铁电存储器（FeRAM或FRAM）是极具有应用前景的一种新型非挥发存储器，它拥有高速随机读写、低电压操作、高耐久度、抗辐照等优点，有望成为下一代主流半导体存储器之一。本论文针对铁电存储器的电路设计技术进行了多方面的研究和尝试，论文主要工作由以下三大部分组成。 论文首先针对铁电存储器嵌入式应用的可测性问题，研究了嵌入式铁电存储器的故障模型、测试方法和测试算法，设计了用于嵌入式铁电存储器的内建自测试（BIST）模块，在这一模块中集成了四种常见的具有较高故障覆盖率的行进测试算法，最后用VHDL语言实现并仿真。 基于0.35µm成熟铁电工艺，本论文参与设计了多款Kbit量级铁电存储芯片并独立完成了具有创新意义的新型三值铁电存储器的全定制设计。主要设计了1Kbit、4Kbit、16Kbit铁电存储器的译码单元、地址缓冲单元及纠错单元（ECC）的电路及版图设计；提出了可显著提高铁电存储器存储密度的新型三值铁电存储器整体架构、阵列排布和工作模式；完成了32bit验证性三值铁电存储芯片的电路及版图设计；对三值铁电存储器的基本功能及可靠性进行了仿真验证，着重考虑了工艺偏差、印迹效应和疲劳效应对三值铁电存储器可靠性的影响。

Ferroelectric Random Access Memory (FeRAM or FRAM) is the new generation novel non-volatile memory with many promising applications. FeRAM has many advantages in high write/read speed, low-voltage operation, high endurance and anti-radicalization, which make FeRAM as one of the primary memory products of next-generation semiconductor memory. This paper investigates and researches in the circuit design techniques for advanced FeRAM which is composed by three main parts. Firstly, ferroelectric memory’s faults modeling, testing methods and testing algorisms are investigated aiming at solving the testability issues in FeRAM’s SOC applications. A programmable Built-in-Self-Test circuit is designed for FeRAM which integrates four conventional March test algorisms. The BIST circuit is implemented and simulated using VHDL language. Based on 0.35µm FeRAM process, several Kbit FeRAM and novel three-level FeRAM are designed. This paper designs the decoder module and error-correcting module for Kbit FeRAM including circuit and layout design. A complete design of 32bit three-level FeRAM is also presented in this paper including the memory architecture, write/read schemes and the reliability analysis. This novel three-level FeRAM improves the density of FeRAM by 1.5 to 3 times compared to traditional 1T1C and 2T2C FeRAM.