随着集成电路规模的不断扩大，工作频率的不断提高，各种便携式设备的不断发展以及能源和环境保护方面的要求，低功耗已经成为集成电路设计中一个必须解决的关键问题。虽然计算机辅助设计（CAD）技术已经在集成电路设计的各个方面得到广泛应用，极大地提高了设计的效率和成功率，但面向低功耗设计的CAD技术在近年来才得到重视和发展。本文按照CMOS数字电路设计流程中的各个设计层次，即从行为级，寄存器传输级直到门级设计，提出了一系列新的进行功耗分析和功耗优化的CAD方法。在门级，本文提出了一种改进的两两相关近似模型对电路网表中节点之间的相关进行建模。通过对相关性划分强弱，减小了紧相关和强相关节点的计算误差，并且按照逻辑深度逐级计算电路的功耗，不仅使计算精度得到了改善，而且使计算的复杂度得到了一定的控制。本文还研究了输入的翻转行为对电路功耗的影响，提出电路的功耗是电路输入信号概率的非对称单峰函数以及功耗与输入翻转概率之间的近似线性关系。针对时序逻辑电路，本文还提出一种电路化简的方法，提高了功耗分析的速度。此外，本文提出了一种基于关键路径的单元尺寸优化方法，即对电路中的某些“关键节点”进行功耗优化和对关键路径中的某些节点同时进行尺寸优化，从而进一步改善电路的功耗延迟积。在寄存器传输级，本文采用信息论中熵的方法对布尔函数的面积和功耗进行估计，首先提出了布尔函数输出熵的一种精确级数展开式，它具有逐级收敛的性质，利用它可以对输出熵进行较为精确的估计。在此基础上，提出了一种新的布尔函数面积和功耗的估计式，使得估计的准确度有了进一步提高。本文还对有限状态机的低功耗状态编码问题进行了研究，采用遗传算法进行并行搜索, 建立了状态编码方案的二进制串表示，并且采用复制、交叉和变异算子进行群体演化，将群体中适应值最大的编码方案作为最后的结果。针对电路面积对功耗的影响，在适应值计算过程中采用了一定的权重。实验结果证明采用遗传算法是很有效的。最后，在行为级，本文提出了一种基于最小能量的算子调度算法，对折叠循环结构的控制数据流图（CDFG）进行算子调度。它可以根据给定的硬件约束或者时间约束，自动对CDFG进行循环折叠，确定完成运算所需的周期数（对硬件约束）或者硬件数目（对时间约束），并且得到满足约束条件的算子调度方案。采用此方法，可以得到较大的功耗优化。本文研究结果表明，设计的抽象层次越高，进行功耗优化所带来的收益也越大，这说明了高层次设计方法学研究的重要性和迫切性，这也是值得进一步深入研究的领域。
Low power has become a main concern in integrated circuits (IC's) design with the continuing increase of IC scale, speedup of operating frequency and development of portable devices. Although CAD techniques have been applied in all aspects of IC design, which greatly increases the design efficiency and possibility of success, the CAD techniques aiming at low power IC design have just been paid attention to and still under development. This dissertation put forward a series of new CAD techniques for power estimation and power optimization according to the hierarchy of CMOS digital circuit design, i.e., from behavioral level to register transfer level, till gate level. At gate level, this dissertation proposes a modified pair-wise correlation model to approximate correlation between nodes in the netlist. Power estimation error of closely/strongly correlated nodes is reduced by classifing the correlation according to its strength. The power estimation is carried on in a stage-by-stage approach, making the complexity of calculation controllable while keeping the precision improved. This dissertation also studies the effect of input transition activities on circuit power, and finds that power is a non-symmetrical single-summit function of input signal probability and a near linear function of input transition probability. For sequential circuits, this dissertation provides a circuit simplification method to improve the speed of power estimation. Besides, this dissertation proposes a critical-path based transistor resizing approach, i.e., perform transistor resizing for some "critical nodes" in the circuit and simultaneous resizing of several nodes in the critical path. This method can further improve the power-delay product of the circuit.At register transfer level, this dissertation takes an entropy approach in information theory to estimate the area and power of boolean functions. An accurate series expansion formula for boolean function output entropy is obtained, which can be used to calculate output entropy accurately due to its gradual convergence property. Based on this formula, a novel area and power estimation formula for boolean functions is proposed with the accuracy of estimation being improved. This dissertation also studies the low-power state encoding for finite state machines. Genetic algorithm (GA) is applied to parallel searching. The binary-cluster representation for encoding scheme is established and the reproduction, crossover and mutation operations are used to carry on the evolution. The best suitable encoding scheme in the population is chosen as the final result. Taking into consideration the effect of circuit area on final power, some weight is introduced in the fitness calculation. The experimental results show that the GA approach is efficient.At last, at the behavioral level, this dissertation proposes a minimal-energy based operator scheduling approach to perform operator scheduling for loop folding CDFG structure. This approach can automatically do loop folding for CDFG based on given hardware or timing constraints, decide the cycles needed (for hardware constraint) or number of hardware required (for timing constraint), and obtain the final scheduling with the constraints being satisfied. An even greater power improvement can be achieved by this method.The results of this dissertation show that the higher the design abstract level, the more we can gain from power optimization, which makes the research on high level design methodology more important and urgent, and it stays open as a field for further study.
