随着硅基互补金属氧化物（Complementary Metal-Oxide Silicon，CMOS）工艺的进步和无线通信的发展，射频通信系统单芯片集成成为趋势。本论文研究了针对无线射频应用的Sigma-Delta分数分频频率合成器，完成了以下工作：　　改进了前人对于锁相环频率合成器的行为级仿真模型，使其可以有效地应用到分数分频频率合成器中，提高了仿真速度。　　对Sigma-Delta分数分频频率合成器中由电荷泵失配引起的带内噪声的增加进行了分析，提供了一种预估此类噪声的方法，并导出了此类噪声的解析计算公式。同时对现有各种用于频率合成器的Sigma-Delta调制器（Sigma-Delta Modulator，SDM）的性能进行了总结，给出了一些根据具体设计要求选择SDM结构的建议，提出了一种用两比特量化的MASH（Multi-Stage Noise Shaping Technology）-1型一阶SDM级联的低杂散MASH-1-1-1型三阶SDM。　　提出了一种提高压控振荡器（Voltage Controlled Oscillator，VCO）性能稳定性的方法，使其在工艺参数、电压以及温度发生变化的时候，电路的性能变化减小。对于我们关心的电路中的晶体管的跨导，经过对补偿的和未经过补偿的电路进行统计后发现，与未采用补偿的电路相比，补偿后的电路的跨导变化范围缩小了26.3%、跨导的标准差降低了41.4%。　　提出了一种可以工作在极低电压下的VCO。在中芯国际0.18 μm CMOS工艺下，对该电路和传统的VCO电路进行了对比验证，除了衬底偏置电压不同以外，两个电路的其它参数均相同，电路仿真结果表明，无论从电源电压还是偏置电流看，本文提出的电路都要优于传统的电路，能在保证电路性能和复杂度基本不变的前提下，使电压降低13%、功耗降低25%。　　提出了一种新型的八固定相位输出的二分频器。它可应用于分频比为7/8的预分频器。本文提出的电路除设计更为简单之外，还有更高的稳定性和更强的抗短脉冲噪声干扰的能力。

With the development of CMOS (Complementary Metal-Oxide Silicon) technology and wireless communications, it has become a general trend to integrate a whole radio-frequency (RF) communication system on a single chip. In this dissertation, the design and analysis of Sigma-Delta fractional-N frequency synthesizer for RF applications is conducted and the principal contributions of this dissertation include: In this dissertation, a modified behavioral model of phase noise and jitter in Sigma-Delta fractional-N phase-locked loop (PLL) frequency synthesizer is proposed, and this model can be used to improve the efficiency of the design of PLL. In this dissertation, the in-band phase noise due to mismatch of charge pump in Sigma-Delta fractional-N frequency synthesizers is analyzed. An efficient method to predict this kind of noise is presented and an analytical equation is proposed to calculate this kind of noise quantitatively. The comparison of the performances of all kinds of Sigma-Delta Modulators (SDM) used in fractional-N frequency synthesizers is presented, and some suggestions for application-based SDM-topology selection for frequency synthesizer is concluded, too. A new MASH (Multi-Stage Noise Shaping Technology)-1-1-1 3rd order SDM with low spur is proposed, which is composed of MASH-1 1st order SDM with 2 bits quantizer. In this dissertation, a simple and successful method for stability enhancement of integrated circuits is presented. When the variation of process parameters, environment temperature, and supply voltage is considered, according simulation result, this method makes the standard deviation of the transconductance of MOSFET 41.4% less than the uncompensated. This kind of method can be used in CMOS LC oscillator design. In this dissertation, an improved ultra-low-voltage VCO is proposed. Being implemented in SMIC (Semiconductor Manufacturing International Corporation) 0.18 μm CMOS process, the proposed VCO can not only be operated by lower supply voltage than a conventional one, but it also consumes less current or power. In another words, a 13% reduction in power supply voltage and a 25% reduction in power consumption have been achieved without any significant loss in circuit performance and complexity. In this dissertation, a novel divided-by-2 circuit is proposed to generate 8 output phases. This circuit is composed of only four serially connected differential latches and phase-pattern uncertainty in conventional circuits is avoided. This feature decreases the logic complexity of phase switching prescalers and improves its noise immunity and stability.